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參數(shù)資料
| 型號： | CXK77B3641AGB |
| 廠商： | Sony Corporation |
| 英文描述： | 4Mb Late Write LVTTL High Speed Synchronous SRAMs (128K x 36Bit)(4M位、寫延遲、高速邏輯收發(fā)（HSTL）、高速同步靜態(tài)RAM (128K x 36位)) |
| 中文描述： | 4Mb的后寫入LVTTL高速（128K的x 36Bit）（4分位，寫延遲，高速邏輯收發(fā)（HSTL），高速同步靜態(tài)隨機(jī)存儲器（128K的× 36位）同步靜態(tài)存儲器） |
| 文件頁數(shù)： | 7/28頁 |
| 文件大?。?/td> | 222K |
| 代理商： | CXK77B3641AGB |
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4Mb, Sync LW, LVTTL, rev 1.2
7 / 28
September 24, 1998
SONY
CXK77B3641AGB / CXK77B1841AGB
Preliminary
Read Operations
These devices support three distinct JEDEC standard read protocols via mode pins M1 and M2.
The mode pins must be set during power-up, and cannot change during SRAM operation.
Mode Select Truth Table
.
When a read operation is initiated, all address and control signals (except G and ZZ) are latched into
input registers on the rising edge of K clock. The latched address is decoded and then used to access a
particular location in the internal memory array. These two events occur regardless which read protocol
is selected. After the memory location is accessed, the read protocol determines when data from that
memory location is driven valid externally.
Register - Register Mode
In Register - Register mode, data is driven valid externally from the subsequent rising edge of K clock,
one full K clock cycle after the address is latched. Data remains valid until at least the next rising edge
of K clock, one full K clock cycle thereafter.
Register - Latch Mode
In Register - Latch mode, data is driven valid externally from the subsequent falling edge of K clock, or,
some minimum amount of time after the address is latched (determined by the access time of the mem-
ory array), whichever is greater. Data remains valid until at least the next falling edge of K clock, ap-
proximately one full K clock cycle thereafter.
Register - Flow Thru Mode
In Register - Flow Thru mode, data is driven valid immediately, some minimum amount of time after the
address is latched (determined by the access time of the memory array). Data remains valid until at least
the next rising edge of K clock, approximately one full K clock cycle thereafter.
Regardless which read protocol is selected, read operations may be initiated consecutively, with no dead
cycles between them.
M1
M2
Register - Register
L
H
Register - Flow Thru
L
L
Register - Latch
H
L
Reserved
H
H
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXK77B1841GB | 4Mb Late Write LVTTL High Speed Synchronous SRAM (256K x 18Bit)(4M位、寫延遲、LVTTL高速同步靜態(tài)RAM (256K x 18位)) |
| CXK77B3611AGB- | High Speed Bi-CMOS Synchronous Static RAM |
| CXK77B3611AGB-5 | High Speed Bi-CMOS Synchronous Static RAM |
| CXK77B3611AGB-6 | High Speed Bi-CMOS Synchronous Static RAM |
| CXK77B3611AGB | High Speed 1MBit Bi-CMOS Synchronous Static RAM(高速1M位、Bi-CMOS同步靜態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXK77B3641GB-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM |
| CXK77B3641GB-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM |
| CXK77K18R320GB | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18) |
| CXK77K18R320GB-3 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18) |
| CXK77K18R320GB-33 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18) |
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