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參數(shù)資料
| 型號(hào)： | CXK77B1841GB |
| 廠商： | Sony Corporation |
| 英文描述： | 4Mb Late Write LVTTL High Speed Synchronous SRAM (256K x 18Bit)(4M位、寫延遲、LVTTL高速同步靜態(tài)RAM (256K x 18位)) |
| 中文描述： | 4Mb的后寫入LVTTL高速同步SRAM（256 × 18位）（4分位，寫延遲，LVTTL高速同步靜態(tài)隨機(jī)存儲(chǔ)器（256 × 18位）） |
| 文件頁數(shù)： | 1/22頁 |
| 文件大?。?/td> | 199K |
| 代理商： | CXK77B1841GB |
256Kx18, Sync LW, LVTTL, rev 4.6
1 / 22
August 12, 1998
CXK77B1841GB
SONY
45/5/6
4Mb Late Write LVTTL High Speed Synchronous SRAM (256K x 18 Organization)
Description
Features
R-R Mode
t
KHKH
/ t
KHQV
4.5ns / 2.4ns
5.0ns / 2.5ns
6.0ns / 3.0ns
R-L, R-FT Modes
t
KHKH
/ t
KHQV
5.5ns / 5.5ns
5.7ns / 5.7ns
6.0ns / 6.0ns
Fast Cycle/Access Time
CXK77B1841
-45
-5 (*)
-6
Note (*): Contact Sony Memory Marketing for availability of “-5” speed bin.
3 synchronous modes of operation, selectable by mode pins:
Register-Register; Register-Latch; Register-Flow Thru;
Single +3.3V power supply: 3.3V
±
5%
Dedicated output supply voltage: V
DDQ
(2.5V to 3.3V typical)
Inputs and outputs are LVTTL/LVCMOS compatible.
Differential clock input (K/K). Clock levels are compatible to PECL, LVTTL and LVCMOS.
All inputs (except asynchronous G and ZZ) and outputs are registered on a single clock edge.
Byte Write capability.
Late Write scheme to eliminate one dead cycle from Read-to-Write transitions.
Self-timed write cycles.
Sleep (power down) mode.
JTAG boundary scan (subset of IEEE standard 1149.1).
119 pin (7x17) Plastic Ball Grid Array (PBGA) package.
The CXK77B1841 is a high speed BiCMOS synchronous static RAM with common I/O pins, organized as 262,144-words by
18-bits. This synchronous SRAM integrates input registers, high speed RAM, output registers/latches, and a one-deep write
buffer onto a single monolithic IC. Three different read protocols - Register-Register (R-R), Register-Latch (R-L), and Register-
Flow Thru (R-FT), and an enhanced write protocol - Late (Delayed) Write (LW), are supported, providing a flexible, high-per-
formance user interface.
All input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the positive edge of K clock.
Read cycles can be controlled in one of three ways - with registered outputs in Register-Register mode, with latched outputs in
Register-Latch mode, or with flow-through outputs in Register-Flow Thru mode. The read protocol is user-selectable through
external mode pins M1 and M2.
Write cycles follow a Late Write protocol, where data is provided to the SRAM one clock cycle after the address and control
signals, eliminating one dead cycle from Read-to-Write transitions. In this scheme, when a write cycle is initiated, the address
and data stored in the SRAM’s write buffer during the previous write cycle are directed to the SRAM’s memory core, while,
simultaneously, the address and data from the current write cycle are stored in the SRAM’s write buffer. In both Register-Latch
and Register-Flow Thru modes, when SW (Global Write Enable) is driven active, the subsequent positive edge of K clock tri-
states the SRAM’s output drivers immediately, allowing consecutive Read-Write-Read operations. The write cycle is internally
self-timed, which eliminates complex off-chip write pulse generation and provides increased flexibility for incoming signals.
Sleep (power down) mode control is provided through the asynchronous ZZ input. 220 MHz operation is obtained from a single
3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.
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