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參數(shù)資料
| 型號： | CXK77B3641AGB |
| 廠商： | Sony Corporation |
| 英文描述： | 4Mb Late Write LVTTL High Speed Synchronous SRAMs (128K x 36Bit)(4M位、寫延遲、高速邏輯收發(fā)（HSTL）、高速同步靜態(tài)RAM (128K x 36位)) |
| 中文描述： | 4Mb的后寫入LVTTL高速（128K的x 36Bit）（4分位，寫延遲，高速邏輯收發(fā)（HSTL），高速同步靜態(tài)隨機(jī)存儲器（128K的× 36位）同步靜態(tài)存儲器） |
| 文件頁數(shù)： | 8/28頁 |
| 文件大?。?/td> | 222K |
| 代理商： | CXK77B3641AGB |
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4Mb, Sync LW, LVTTL, rev 1.2
8 / 28
September 24, 1998
SONY
CXK77B3641AGB / CXK77B1841AGB
Preliminary
Write Operations
These devices follow a Late Write protocol, where, during a write operation, data is provided to the
SRAM one clock cycle after the address and control signals, eliminating the need for one of the bus-
turnaround cycles required when changing from a read to a write operation. The Late Write function is
controlled internally by using a dedicated one-deep write buffer to store the address and data signals as-
sociated with the current write operation. The buffered data is not actually written to the memory array
until the next write operation is initiated.
When a write operation is initiated, all address and control signals (except G and ZZ) are latched into
input registers on the rising edge of K clock. Also at this time, any valid data currently stored in the one-
deep write buffer (associated with the previous write operation) is written to the memory array. On the
subsequent rising edge of K clock, the data and address signals for the current write operation are stored
in the write buffer. This write pipeline mechanism allows write operations to be initiated consecutively,
with no dead cycles between them.
Note: In order to maintain coherency, if a read operation is initiated to the same address as that of the
last write operation (i.e. to the address of the write operation currently stored in the write buffer), read
data is provided from the write buffer instead of the memory array. If only some of the bytes of data in
the write buffer are valid, those bytes of data that are valid are provided from the write buffer, and those
bytes of data that are invalid are provided from the memory array.
Sleep (Power Down) Mode
Sleep (power down) mode is provided through the asynchronous input signal ZZ. When ZZ is asserted
(high), the output drivers will go to a Hi-Z state, and the SRAM will begin to draw standby current. Con-
tents of the memory array will be preserved. An enable time (t
ZZE
) must be met before the SRAM is
guaranteed to be in sleep mode, and a recovery time (t
ZZR
) must be met before the SRAM can resume
normal operation.
Power-Up Sequence
Power supplies must power up in the following sequence: V
SS
, V
DD
, V
DDQ
, V
REF
, and Inputs.
V
DDQ
must never exceed V
DD
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CXK77B1841GB | 4Mb Late Write LVTTL High Speed Synchronous SRAM (256K x 18Bit)(4M位、寫延遲、LVTTL高速同步靜態(tài)RAM (256K x 18位)) |
| CXK77B3611AGB- | High Speed Bi-CMOS Synchronous Static RAM |
| CXK77B3611AGB-5 | High Speed Bi-CMOS Synchronous Static RAM |
| CXK77B3611AGB-6 | High Speed Bi-CMOS Synchronous Static RAM |
| CXK77B3611AGB | High Speed 1MBit Bi-CMOS Synchronous Static RAM(高速1M位、Bi-CMOS同步靜態(tài)RAM) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CXK77B3641GB-5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM |
| CXK77B3641GB-6 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x36 Fast Synchronous SRAM |
| CXK77K18R320GB | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18) |
| CXK77K18R320GB-3 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18) |
| CXK77K18R320GB-33 | 制造商:SONY 制造商全稱:Sony Corporation 功能描述:32Mb LW R-R HSTL High Speed Synchronous SRAM (2Mb x 18) |
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