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參數(shù)資料
| 型號： | COP885BC |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 8-Bit CMOS ROM Based Microcontrollers with 2k Memory, Comparators, and CAN Interface(8位基于CMOS ROM帶2K存儲器，比較器和CAN接口的微控制器) |
| 中文描述： | 8位的CMOS基于ROM與2K內(nèi)存，比較器和CAN接口（8位基于ROM的帶2K的CMOS存儲器，比較器和CAN微控制器接口的微控制器） |
| 文件頁數(shù)： | 48/57頁 |
| 文件大小： | 677K |
| 代理商： | COP885BC |
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Addressing Modes
(Continued)
TRANSFER OF CONTROL ADDRESSING MODES
Relative
This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new pro-
gram location. JP has a range from 31 to +32 to allow a
1-byte relative jump (JP + 1 is implemented by a NOP in-
struction). There are no “pages” when using JP, since all 15
bits of PC are used.
Absolute
This mode is used with the JMP and JSR instructions, with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any loca-
tion in the current 4k program memory segment.
Absolute Long
This mode is used with the JMPL and JSRL instructions, with
the instruction field of 15 bits replacing the entire 15 bits of
the program counter (PC). This allows jumping to any loca-
tion up to 32k in the program memory space.
Indirect
This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits of
PC) for accessing a location in the program memory. The
contents of this program memory location serve as a partial
address (lower 8 bits of PC) for the jump to the next instruc-
tion.
Note:
The VIS is a special case of the Indirect Transfer of Control addressing
mode, where the double byte vector associated with the interrupt is
transferred from adjacent addresses in the program memory into the
program counter (PC) in order to jump to the associated interrupt ser-
vice routine.
Instruction Set
Register and Symbol Definition
Registers
A
B
X
SP
PC
PU
PL
C
HC
GIE
8-Bit Accumulator Register
8-Bit Address Register
8-Bit Address Register
8-Bit Stack Pointer Register
15-Bit Program Counter Register
Upper 7 Bits of PC
Lower 8 Bits of PC
1-Bit of PSW Register for Carry
1-Bit of PSW Register for Half Carry
1-Bit of PSW Register for Global Interrupt
Enable
Interrupt Vector Upper Byte
Interrupt Vector Lower Byte
VU
VL
Symbols
[B]
[X]
MD
Mem
Meml
Memory Indirectly Addressed by B Register
Memory Indirectly Addressed by X Register
Direct Addressed Memory
Direct Addressed Memory or [B]
Direct Addressed Memory or [B] or
Immediate Data
8-Bit Immediate Data
Register Memory: Addresses F0 to FF
(Includes B, X and SP)
Bit Number (0 to 7)
Loaded with
Exchanged with
Imm
Reg
Bit
←
C
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48
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