參數(shù)資料
型號(hào)： COP885BC
廠商： National Semiconductor Corporation
英文描述： 8-Bit CMOS ROM Based Microcontrollers with 2k Memory, Comparators, and CAN Interface(8位基于CMOS ROM帶2K存儲(chǔ)器，比較器和CAN接口的微控制器)
中文描述： 8位的CMOS基于ROM與2K內(nèi)存，比較器和CAN接口（8位基于ROM的帶2K的CMOS存儲(chǔ)器，比較器和CAN微控制器接口的微控制器）
文件頁(yè)數(shù)： 41/57頁(yè)
文件大?。?/td> 677K
代理商： COP885BC
Interrupts
(Continued)
TABLE 9. Interrupt Vector Table
Arbitration
Ranking
1
2
3
4
Source
Vector Address
Hi-Low Byte
0yFE–0yFF
0yFC–0yFD
0yFA–0yFB
0yF8–0yF9
Software Trap
Reserved
CAN Receive
CAN Error
(transmit/receive)
CAN Transmit
Pin G0 Edge
IDLE Timer Underflow
Timer T1A/Underflow
Timer T1B
MlCROWIRE/PLUS
PWM timer
Reserved
Reserved
Reserved
Port L/Wake Up
Default VIS Interrupt
5
6
7
8
9
0yF6–0yF7
0yF4–0yF5
0yF2–0yF3
0yF0–0yF1
0yEE–0yEF
0yEC–0yED
0YEA–0yEB
0yE8–0yE9
0yE6–0yE7
0yE4–0yE5
0yE2–0yE3
0yE0–0yE1
10
11
12
13
14
15
16
Note 18:
y is VIS page, y
≠
0
If, by accident, a VIS gets executed and no interrupt is ac-
tive, then the PC (Program Counter) will branch to a vector
located at 0yE0-0yE1.
VIS Execution
When the VIS instruction is executed it activates the arbitra-
tion logic. The arbitration logic generates an even number
between E0 and FE (E0, E2, E4, E6 etc...) depending on
which active interrupt has the highest arbitration ranking at
the time of the 1st cycle of VIS is executed. For example, if
the software trap interrupt is active, FE is generated. If the
external interrupt is active and the software trap interrupt is
not, then FAis generated and so forth. If the only active inter-
rupt is software trap, than E0 is generated. This number re-
places the lower byte of the PC. The upper byte of the PC re-
mains unchanged. The new PC is therefore pointing to the
vector of the active interrupt with the highest arbitration rank-
ing. This vector is read from program memory and placed
into the PC which is now pointed to the 1st instruction of the
service routine of the active interrupt with the highest arbitra-
tion ranking.
Figure 36 illustrates the different steps performed by the VIS
instruction. Figure 37 shows a flowchart for the VIS instruc-
tion.
The non-maskable interrupt pending flag is cleared by the
RPND (Reset Non-Maskable Pending Bit) instruction (under
certain conditions) and upon RESET.
C
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41
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