參數(shù)資料
型號(hào): COP885BC
廠商: National Semiconductor Corporation
英文描述: 8-Bit CMOS ROM Based Microcontrollers with 2k Memory, Comparators, and CAN Interface(8位基于CMOS ROM帶2K存儲(chǔ)器,比較器和CAN接口的微控制器)
中文描述: 8位的CMOS基于ROM與2K內(nèi)存,比較器和CAN接口(8位基于ROM的帶2K的CMOS存儲(chǔ)器,比較器和CAN微控制器接口的微控制器)
文件頁(yè)數(shù): 38/57頁(yè)
文件大?。?/td> 677K
代理商: COP885BC
Comparators
(Continued)
CMP1EN
Enables comparator 1 (“1”=enable). If compara-
tor 1 is disabled the associated L-pins can be
used as standard I/O.
Reserved This bit is reserved and should be zero.
The Comparator Select/Control bits are cleared on RESET
(the comparator is disabled). To save power, the program
should also disable the comparator before the device enters
the HALT mode.
The Comparator rise and fall times are symmetrical. The
user program must set up the Configuration and Data regis-
ters of the L port correctly for comparator Inputs/Output.
Interrupts
INTRODUCTION
Each device supports eleven vectored interrupts. Interrupt
sources include Timer 0, Timer 1, Port L Wakeup, Software
Trap, MICROWIRE/PLUS, and External Input.
All interrupts force a branch to location 00FF Hex in program
memory. The VIS instruction may be used to vector to the
appropriate service routine from location 00FF Hex.
The Software trap has the highest priority while the default
VIS has the lowest priority.
Each of the 11 maskable inputs has a fixed arbitration rank-
ing and vector.
Figure 35 shows the Interrupt Block Diagram.
DS012067-36
The BOXED area shows logic from PWM Timer. Comparator 2 output (CMP2OE) must be disabled in order to use PWM0 output.
FIGURE 34. Comparator Block
C
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