參數(shù)資料
型號: COP885BC
廠商: National Semiconductor Corporation
英文描述: 8-Bit CMOS ROM Based Microcontrollers with 2k Memory, Comparators, and CAN Interface(8位基于CMOS ROM帶2K存儲器,比較器和CAN接口的微控制器)
中文描述: 8位的CMOS基于ROM與2K內(nèi)存,比較器和CAN接口(8位基于ROM的帶2K的CMOS存儲器,比較器和CAN微控制器接口的微控制器)
文件頁數(shù): 22/57頁
文件大?。?/td> 677K
代理商: COP885BC
CAN Interface Block
(Continued)
Fully automatic transmission on error is supported for mes-
sages not longer than two bytes. Messages which are longer
than two bytes have to be processed by software.
The interface is compatible with CAN Specification 2.0 part
B, without the capability to receive/transmit extended
frames. Extended frames on the bus are checked and ac-
knowledged according to the CAN specification.
The maximum bus speed achievable with the CAN interface
is a function of crystal frequency, message length and soft-
ware overhead. The device can support a bus speed of up to
1 Mbit/s with a 10 MHz oscillator and 2 byte messages. The
1 Mbit/s bus speed refers to the rate at which protocol and
data bits are transferred on the bus. Longer messages re-
quire slower bus speeds due to the time required for soft-
ware intervention between data bytes. The device will sup-
port a maximum of 125k bit/s with eight byte messages and
a 10 MHz oscillator.
Functional Block Description of
the CAN Interface
Interface Management Logic (IML)
The IML executes the CPU’s transmission and reception
commands and controls the data transfer between CPU,
Rx/Tx and CAN registers. It provides the CAN Interface with
Rx/Tx data from the memory mapped Register Block. It also
sets and resets the CAN status information and generates
interrupts to the CPU.
Bit Stream Processor (BSP)
The BSP is a sequencer controlling the data stream between
The Interface Management Logic (parallel data) and the bus
line (serial data). It controls the transceive logic with regard
to reception and arbitration, and creates error signals ac-
cording to the bus specification
DS012067-49
FIGURE 17. CAN Interface Block Diagram
C
www.national.com
22
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