- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379931 > COP885BC (National Semiconductor Corporation) 8-Bit CMOS ROM Based Microcontrollers with 2k Memory, Comparators, and CAN Interface(8位基于CMOS ROM帶2K存儲器，比較器和CAN接口的微控制器) PDF資料下載
參數(shù)資料
| 型號： | COP885BC |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 8-Bit CMOS ROM Based Microcontrollers with 2k Memory, Comparators, and CAN Interface(8位基于CMOS ROM帶2K存儲器，比較器和CAN接口的微控制器) |
| 中文描述： | 8位的CMOS基于ROM與2K內(nèi)存，比較器和CAN接口（8位基于ROM的帶2K的CMOS存儲器，比較器和CAN微控制器接口的微控制器） |
| 文件頁數(shù)： | 24/57頁 |
| 文件大?。?/td> | 677K |
| 代理商： | COP885BC |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁
Functional Block Description of the CAN Interface
(Continued)
In the case of an interrupt driven CAN interface, the calculation of the actual t
LOAD
time would be done as follows:
INT:
; Interrupt latency = 7 tc = 7 μs
PUSH A
;
3 tc = 3 μs
LD
A,AB
;
2 tc = 2 μs
PUSH A
;
3 tc = 3 μs
VIS
;
5 tc = 5 μs
CANTX:
; 20 tc = μs to this point
.
; additional time for instructions which check
.
; status prior to reloading the transmit data
.
; registers with subsequent data bytes.
LD
TXD2,DATA
.
.
.
Interrupt driven programs use more time than programs
which poll the TBE flag, however programs which operate at
lower baud rates (which are more likely to be sensitive to this
issue) have more time for interrupt response.
Output Drivers/Input Comparators
The output drivers/input comparators are the physical inter-
face to the bus. Control bits are provided to TRI-STATE the
output drivers.
A dominant bit on the bus is represented as a “0” in the data
registers and a recessive bit on the bus is represented as a
“1” in the data registers.
TABLE 3. Bus Level Definition
Bus Level
Pin Tx0
drive low
(GND)
TRI-STATE
Pin Tx1
drive high
(V
CC
)
TRI-STATE
Data
“dominant”
0
“recessive”
1
Register Block
The register block consists of fifteen 8-bit registers which are
described in more detail in the following paragraphs.
Note:
The contents of the receiver related registers RxD1, RxD2, RDLC,
RIDH and RTSTAT are only changed if a received frame passes the
acceptance filter or the Receive Identifier Acceptance Filter bit (RIAF)
is set to accept all received messages.
TRANSMIT DATA REGISTER 1 (TXD1) (Address
X’00B0)
The Transmit Data Register 1 contains the first data byte to
be transmitted within a frame and then the successive odd
byte numbers (i.e., bytes number 1,3,..,7).
TRANSMIT DATA REGISTER 2 (TXD2)(Address X’00B1)
The Transit Data Register 2 contains the second data byte to
be transmitted within a frame and then the successive even
byte numbers (i.e., bytes number 2,4,..,8).
TRANSMIT DATA LENGTH CODE AND IDENTIFIER
LOW REGISTER (TDLC) (Address X’00B2)
TID3
Bit 7
This register is read/write.
TID3..TIDO
The transmit identifier is composed of eleven bits in total, bits
3 to 0 of the TID are stored in bits 7 to 4 of this register.
TID2
TID1
TID0
TDLC3
TDLC2
TDLC1
TDLC0
Bit 0
Transmit Identifier Bits 3..0 (lower 4 bits)
TDLC3..TDLC0 Transmit Data Length Code
These bits determine the number of data bytes to be trans-
mitted within a frame. The CAN specification allows a maxi-
mum of eight data bytes in any message.
TRANSMIT IDENTIFIER HIGH (TID) (Address X’00B3)
TRTR
Bit 7
This register is read/write.
TRTR
Transmit Remote Frame Request
This bit is set if the frame to be transmitted is a remote frame
request.
TID10..TID4
Transmit Identifier Bits 10 .. 4 (higher 7 bits)
Bits TID10..TID4 are the upper 7 bits of the 11 bit transmit
identifier.
TID10
TID9
TID8
TID7
TID6
TID5
TID4
Bit 0
RECEIVER DATA REGISTER 1 (RXD1) (Address
X’00B4)
The Receive Data Register 1 (RXD1) contains the first data
byte received in a frame and then successive odd byte num-
bers (i.e., bytes 1, 3,..7). This register is read-only.
RECEIVE DATA REGISTER 2 (RXD2) (Address X’00B5)
The Receive Data Register 2 (RXD2) contains the second
data byte received in a frame and then successive even byte
numbers (i.e., bytes 2,4,..,8). This register is read-only.
REGISTER DATA LENGTH CODE AND IDENTIFIERLOW
REGISTER (RIDL) (Address X’00B6)
RID3
Bit 7
This register is read only.
RID3..RID0
The RID3..RID0 bits are the lower four bits of the eleven bit
long Receive Identifier. Any received message that matches
the upper 7 bits of the Receive Identifier (RID10..RID4) is ac-
cepted if the Receive IdentifierAcceptance Filter (RIAF) bit is
set to zero.
RDLC3..RDLC0 Receive Data Length Code bits
The RDLC3..RDLC0 bits determine the number of data
bytes within a received frame.
RID2
RID1
RID0
RDLC3
RDLC2
RDLC1
RDLC0
Bit 0
Receive Identifier bits (lower four bits)
C
www.national.com
24
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| COP884CF | 8-Bit CMOS ROM Based Microcontrollers with 4k Memory and A/D Converter |
| COP884CG | Dual Low-Voltage Rail-to-Rail Output Operational Amplifier 8-MSOP -40 to 125 |
| COP884CS | Dual Low-Voltage Rail-to-Rail Output Operational Amplifier 8-SOIC -40 to 125 |
| COP884EG | Dual Low-Voltage Rail-to-Rail Output Operational Amplifier 8-SOIC -40 to 125 |
| COP884EK | Dual Low-Voltage Rail-to-Rail Output Operational Amplifier 8-TSSOP -40 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| COP885BC-XXX/WM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| COP888CF | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS ROM Based Microcontrollers with 4k Memory and A/D Converter |
| COP888CFMHD-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| COP888CFMHD-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
| COP888CFMHEL-1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復。