參數(shù)資料
型號(hào): COP885BC
廠商: National Semiconductor Corporation
英文描述: 8-Bit CMOS ROM Based Microcontrollers with 2k Memory, Comparators, and CAN Interface(8位基于CMOS ROM帶2K存儲(chǔ)器,比較器和CAN接口的微控制器)
中文描述: 8位的CMOS基于ROM與2K內(nèi)存,比較器和CAN接口(8位基于ROM的帶2K的CMOS存儲(chǔ)器,比較器和CAN微控制器接口的微控制器)
文件頁(yè)數(shù): 25/57頁(yè)
文件大?。?/td> 677K
代理商: COP885BC
Functional Block Description of
the CAN Interface
(Continued)
RECEIVE IDENTIFIER HIGH (RID) (Address X’00B7)
Reserved
Bit 7
This register is read/write.
Reserved Bit 7 is reserved and must be zero.
RID10..RID4 Receive Identifier bits (upper bits)
The RID10...RID4 bits are the upper 7 bits of the eleven bit
long Receive Identifier. If the Receive Identifier Acceptance
Filter (RIAF) bit (see CBUS register) is set to zero, bits 4 to
10 of the received identifier are compared with the mask bits
of RID4..RID10. If the corresponding bits match, the mes-
sage is accepted. If the RIAF bit is set to a one, the filter
function is disabled and all messages, independent of iden-
tifier, will be accepted.
RID10
RID9
RID8
RID7
RID6
RID5
RID4
Bit 0
CAN PRESCALER REGISTER (CSCAL) (Address
X’00B8)
CKS7
CKS6
CKS5
CKS4
CKS3
CKS2
CKS1
CKS0
Bit 7
Bit 0
This register is read/write.
CKS7..0
Prescaler divider select.
The resulting clock value is the CAN Prescaler clock.
CAN BUS TIMING REGISTER (CTIM) (00B9)
PPS2
PPS1
PPS0
PS2
PS1
PS0
Reserved
Reserved
Bit 7
This register is read/write.
PPS2..PPS0
The PPS2..PPS0 bits determine the length of the propaga-
tion delay in Prescaler clock cycles (PSC) per bit time. (For
a more detailed discussion of propagation delay and phase
segments, see SYNCHRONIZATION.)
PS2..PS0
Phase Segment 1, bits 2..0
The PS2..PS0 bits fix the number of Prescaler clock cycles
per bit time for phase segment 1 and phase segment 2. The
PS2..PS0 bits also set the synchronization Jump Width to a
value equal to the lesser of: 4 PSC, or the length of PS1/2
(Min: 4 l length of PS1/2).
Bit 0
Propagation Segment, bits 2..0
TABLE 4. Synchronization Jump Width
Length of
Phase
Segment
1
2
1 t
can
2 t
can
3 t
can
4 t
can
5 t
can
6 t
can
7 t
can
8 t
can
Synchronization
Jump Width
PS2
PS1
PS0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1 t
can
2 t
can
3 t
can
4 t
can
4 t
can
4 t
can
4 t
can
4 t
can
LENGTH OF TIME SEGMENTS (See Figure 31)
The Synchronization Segment is 1 CAN Prescaler clock
(PSC)
The Propagation Segment can be programmed (PPS) to
be 1,2...,8 PSC in length.
Phase Segment 1 and Phase Segment 2 are program-
mable (PS) to be 1,2,..,8 PSC long.
Note:
(BTL settings at high speed; PSC = 0) Due to the on-chip delay from
the rx-pins through the receive comparator (worst case assumption: 3
clocks delay * 2 (devices on the bus) + 1 tx delay) the user needs to set
the sample point to (2*3 + 1) i.e., 7 CKI clocks to ensure correct com-
munication on the bus under all circumstances. With prescaler settings
of 0 this is a given (i.e., no caution has to be applied).
Example: for 1 Mbit CTIM = b’10000100 (PSS = 5; PS1 = 2). Example
for 500 kbit CTIM = b’01011100 (PPS = 3; PS1 = 8). all at 10 MHz
CKI and CSCAL = 0.
CAN BUS CONTROL REGISTER (CBUS) (00BA)
Re-
RIAF
TxEN1
TxEN0
RxREF1
RxREF0
Re-
FMOD
served
served
Bit 7
Reserved This bit is reserved and must be zero.
RIAF
Receive identifier acceptance filter bit
If the RIAF bit is set to zero, bits 4 to 10 of the received iden-
tifier are compared with the mask bits of RID4..RID10 and if
the corresponding bits match, the message is accepted. If
the RIAF bit is set to a one, the filter function is disabled and
all messages independent of the identifier will be accepted.
TxEN0, TxEN1 TxD Output Driver Enable
Bit 0
TABLE 5. Output Drivers
TxEN1
0
TxEN0
0
Output
Tx0, Tx1 TRI-STATE, CAN
input comparator disabled
Tx0 enabled
Tx1 enabled
Tx0 and Tx1 enabled
0
1
1
1
0
1
Bus synchronization of the device is done in the following
way:
If the output was disabled (TxEN1, TxEN0 = “0”) and either
TxEN1 or TxEN0, or both are set to 1, the device will not start
transmission or reception of a frame until eleven consecutive
“recessive” bits have been received. Resetting the TxEN1
and TxEN0 bits will disable the output drivers and the CAN
input comparator. All other CAN related registers and flags
will be unaffected. It is recommended that the user reset the
TxEN1 and TxEN0 bits before switching the device into the
HALT mode (the CAN receive wakeup will still work) in order
to reduce current consumption and to assure a proper resy-
chronization to the bus after exiting the HALT mode.
Note:
A “bus off” condition will also cause Tx0 and Tx1 to be at TRI-STATE
(independent of the values of the TxEN1 and TxEN0 bits).
RXREF1 Reference voltage applied to Rx1 if bit is set
RXREF0 Reference voltage applied to Rx0 if bit is set
FMOD
Fault Confinement Mode select
Setting the FMOD bit to “0” (default after power on reset) will
select the Standard Fault Confinement mode. In this mode
the device goes from “bus off” to “error active” after monitor-
ing 128*11 recessive bits (including bus idle) on the bus. This
mode has been implemented for compatibility with existing
solutions. Setting the FMOD bit to “1” will select the En-
hanced Fault Confinement mode. In this mode the device
goes from “bus off” to “error active” after monitoring 128
“good” messages, as indicated by the reception of 11 con-
C
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