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參數(shù)資料
| 型號： | CIP3250A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費家電 |
| 英文描述： | Component Interface Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 9/44頁 |
| 文件大?。?/td> | 326K |
| 代理商： | CIP3250A |
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ADVANCE INFORMATION
CIP 3250A
9
Micronas
the polarity of the Fast Blank signal can be changed via
I
2
C
register
<12>MIXAMP.
<11>FBLOFF influences the phase delay between the
RGB path and the Fast Blank signal (see Fig. 2
–
4).
The
I
2
C
register
Additionally, a delay of
–
1 to 2 clocks between the Fast
Blank signal and the RGB-path is programmable via I
2
C
register <16>FBLDEL. By selecting a positive delay,
shadowing of characters can be obtained, if the back-
ground color of the RGB-path is set to black.
With the built-in linear mixer, the CIP 3250A is able to
support simple AB roll techniques between analog input
(A) and digital YUV input (B):
VideoOut = A * (1
–
FBLMIX/32) + B * FBLMIX/32,
controllable via the Fast Blank signal (FBL):
FBLMIX =
INT
[(FBL
–
FBLOFF)* MIXAMP/2] + 16,
with FBL of values from 0 to 63. The mixing coefficient
FBLMIX resolves 32 steps within the range from 0 to 32
(dependent on step response chosen via I
2
C register
<12>MIXAMP) (see Fig. 2
–
4).
When the I
2
C register bit <16>FBLCLP is enabled, the
soft mixer operates independently of the analog Fast
Blank input. FBL is clamped to digital 31 (see Fig. 2
–
4).
Mixing between RGB-path and YUV-path is controllable
via the I
2
C register <11>FBLOFF.
fbloff
mixamp
32
0
6
I
2
C Registers
Fig. 2–4:
Fast Blank Processing
FBLMIX
1/2
6
FBL (0...63)
fblclp
31
16
0
1
Select the linear mixer or the nonlinear mixer via I
2
C reg-
ister <12>SELLIN. If the nonlinear mixer is selected, a
dynamic delay control of the analog RGB/YUV input can
be chosen, to avoid edge artefacts of the RGB/YUV sig-
nal (e.g. shading), during transition time of Fast Blank
signal with the I
2
C register <12>CTRLDLY.
In some applications, it is desired to disable the control
by the Fast Blank signal and to pass through the digital
YUVin path or the analog RGB/YUV path. This is pos-
sible by adequately programming the I
2
C registers
<06>PASSYUV and <11>PASSRGB (Table 2
–
1).
Table 2–1:
Source selection of soft mixer
<11>
PASSRGB
<06>
PASSYUV
Fast Blank
signal
Source
0
X
X
RGB
1
0
MIX
YUV/RGB
1
1
X
YUV
X: don
’
t care
2.7.2. Fast Blank Monitor
Bits 0 to 3 of I
2
C register <27> are monitoring the analog
Fast Blank input. Reading I
2
C register <27> Fig. 2
–
5 dis-
plays the contents depending on the analog FBL input
signal.
Fig. 2–5:
Fast Blank Monitor
analog fast
blank input
<27>FBLSTAT
<27>FBLRISE
<27>FBLFALL
<27>FBLHIGH
0
1
1
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
1
0
reading I
2
C
register <27>
2.8. FSY Front Sync and AVI Active Video In
–
DIGIT 2000 chroma sync detection
–
DIGIT 2000 throughput of 72-bit data and clock
–
skew data input for DIGIT 2000
–
skew data input for DIGIT 3000
–
HSYNC as timing reference for clamping pulse gener-
ator
–
active video input to indicate valid video data and to
synchronize chroma multiplex for DIGIT 3000
The FSY input and the AVI input are used to supply all
synchronization information necessary. Three basic
modes of operation can be selected via I
2
C registers
<06>D2KIN, <17>D2KSYNC, <17>SYNCSIM, and
<17>P72BEN.
In a DIGIT 2000 system environment, the CIP 3250A re-
ceives the synchronization information at the FSY input
via the DIGIT 2000 SKEW-protocol. The AVI Input may
be connected to ground GND or VDD (see section
2.14.).
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