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參數(shù)資料
| 型號(hào)： | CIP3250A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Component Interface Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 20/44頁 |
| 文件大?。?/td> | 326K |
| 代理商： | CIP3250A |
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ADVANCE INFORMATION
CIP 3250A
20
Micronas
Table 2–10:
I
2
C-Bus operation, continued
Sub-
Address
(decimal)
Label
Bit No.
(LSB = 0)
Typical
Operation
Value
Function
I
2
C registers for OUTPUT FORMATTER
15
YUVO
3
1
select video component output format
0 = output formater off (i.e. RGB or YUV output with format 4:4:4)
1 = output formater on (i.e. YUV output with format 4:2:2 or 4:1:1)
16
ADD16Q
2
1
black level of Y (luma) output
0 = Convert Y black level at output from ITU-R 601 Standard
to DIGIT 2000 Standard (digital 32)
1 = Y black level at output unchanged
15
MOD411ON
2
0
UV (chroma) output format
0 = 4:2:2
1 = 4:1:1
15
BINO
4
0
UV (chroma) sign of output format
0 = two
’
s complement
1 = binary offset
15
CDEL
1
–
0
0
select UV (chroma) output sample from 4:4:4 format
(0...3)
15
IND
5
1
UV (chroma) output format
0 = DIGIT 2000
1 = DIGIT 3000 / orthogonal
15
UVSW
7
0
UV (chroma) multiplex of output format
0 = DIGIT 3000 4:2:2 / DIGIT 2000 4:1:1 / orthogonal 4:1:1
1 = DIGIT 2000 4:2:2
15
DTI
6
0
UV (chroma) output format
0 = DIGIT 3000 4:2:2 / DIGIT 2000 4:1:1 / orthogonal 4:1:1
1 = DIGIT 2000 4:2:2
16
YDEL
4
–
3
0
adjust Y (luma) output delay in reference to UV (chroma) output
(0...3) clocks
16
DL422Y
1
0
additional Y (luma) output delay
(0...1) clocks (DIGIT 3000 4:2:2 / MAC)
16
DL422C
0
0
additional UV (chroma) output delay
(0...1) clocks (DIGIT 3000 4:2:2 / MAC)
I
2
C registers for SKEW FILTER
04
SKWON
3
0
skew correction
0 = off
1 = on
04
SKWCBS
2
1
skew filter active for
0 = DIGIT 2000 pixel orthogonalization
1 = DIGIT 3000 pixel orthogonalization
20
SKEWLAT
7
–
0
0
latch time for sub-pixel skew value (from FSY-/SKEW-protocol) to ad-
just the processing delays of video data to H-sync (see Fig. 2
–
13)
(0...255)*2 clocks
I
2
C registers for PRIO
14
PRIOEN
7
1
access to Picture Bus (GL, RC, B output)
0 = disabled (Picture Bus is tristate)
1 = enabled (access to Picture Bus possible)
09
PRIOSRC
0
1
Source for PRIO request
0 = PRIO request only if AVO is active
1 = PRIO request always independent of AVO
14
PRIOID
6
–
7
set PRIO priority
(0...7)
13
OVR
7
–
0
0
override value for PRIO-interface
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