參數(shù)資料
型號(hào)： CIP3250A
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
元件分類： 消費(fèi)家電
英文描述： Component Interface Processor
中文描述： SPECIALTY CONSUMER CIRCUIT, PQCC68
封裝： PLASTIC, LCC-68
文件頁(yè)數(shù)： 4/44頁(yè)
文件大小： 326K
代理商： CIP3250A
ADVANCE INFORMATION
CIP 3250A
4
Micronas
Component Interface Processor
Release Notes: Revision bars indicate significant
changes to the previous edition.
1. Introduction
The CIP 3250A is a new CMOS IC that contains on a
single chip the entire circuitry to interface analog YUV/
RGB/Fast Blank to a digital YUV system. The Fast Blank
signal is used to control a soft mixer between the digi-
tized RGB and an external digital YUV source. The CIP
supports various output formats such as YUV
4:1:1/4:2:2 or RGB 4:4:4.
Together with the DIGIT 3000 (e.g. VPC 32xxA) or DIGIT
2000 (e.g. DTI 2250), an interface to a TV-scanrate con-
version circuit and/or multi-media frame buffer can be
obtained.
1.1. Block Diagram
The CIP 3250A contains the following main functional
blocks (see Fig.1–1):
– analog input for RGB or YUV and Fast Blank
– triple 8 bit analog to digital converters for RGB/YUV
with internal programmable clamping
– single 6 bit analog to digital converter for Fast Blank
signal
– digital matrix RGB
YUV (Y, B–Y, R–Y)
– luma contrast and brightness correction for signals
from analog input
– color saturation and hue correction for signals from
analog input
– digital input for DIGIT 2000 or DIGIT 3000 formats
– digital interpolation to 4:4:4 format
– high quality soft mixer controlled by Fast Blank signal
– programmable delays to match digital YUVin and ana-
log RGB/YUV
– variable low pass filters for YUV output
– digital output in DIGIT 2000 and DIGIT 3000 formats,
as well as RGB 4:4:4
– I
2
C bus interface
– clock frequency 13.5...20.25 MHz
1.2. System Configurations
The following figures, 1–2 and 1–3, show different basic
system applications for the CIP 3250A in the DIGIT 3000
environment. Beyond that, a stand alone application
(figure 1–4) also shows the flexibility of the CIP 3250A
in implementing simple analog video interfaces to digital
standards.
YUV 4:1:1
YUV 4:2:2
R/V
MATRIX
I2C
interface
G/Y
B/U
FSY
interface
clock
buffer
FSY
CLK
I2C
Bus
FBL
ADC
Format
Conversion
4:4:4
CT
BR
SAT
SOFT
MIXER
(4:4:4)
Adjustable
LPF
YUV 4:1:1
YUV 4:2:2
RGB 4:4:4
Fig. 1–1:
Block diagram of the CIP 3250A Component Interface Processor
(on/off)
Format
Conversion
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