參數(shù)資料
型號： CIP3250A
廠商： MICRONAS SEMICONDUCTOR HOLDING AG
元件分類： 消費(fèi)家電
英文描述： Component Interface Processor
中文描述： SPECIALTY CONSUMER CIRCUIT, PQCC68
封裝： PLASTIC, LCC-68
文件頁數(shù)： 17/44頁
文件大?。?/td> 326K
代理商： CIP3250A
ADVANCE INFORMATION
CIP 3250A
17
Micronas
Table 2–9:
The I
2
C-bus addresses of the CIP 3250A
– Device Address: 6E Hex
(7 bit, R/W bit omitted, see Sec. 2.16.)
MIXAMP
amplification of Fast Blank amplitude
1
MSB
7
6
5
4
3
2
1
0
LSB
Bit
No.
Sub.
00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
NOISSU
noise shaping of U
–
SATU
saturation multiplier of U
32
NOISSV
noise shaping of V
–
SATV
saturation multiplier of V
32
NOISSY
noise shaping of Y
–
SATY
contrast multiplier of Y
32
BRY
brightness correction of Y
0
CTenable
1
menable
1
skeenable
–
SMODE
saturation mode
0
CLSEL
clamping offset for Y
0
SKWCBS
skew filter mode
–
ATST
testbits
0
LPFLUM
luma low pass filter selection
–
PASSYUV
soft mixer control
0
D2KIN
indigital YUVin
–
DELAYU
UV format of YUVin
–
HALFOUT
oduration
0
CYLUM1
Y low pass filter
–
CYLUM2
Y low pass filter
–
CYCHR1
UV low pass filter
–
CYCHR2
UV low pass filter
–
LPFCHR
chroma low pass filter selection
–
–
TESTCLP
test clamping
0
YUV
analog input select
0
SE_4_8Q
analog gain control
0
SELAMP
analog gain control
0
CLMPOFS
RGB clamping offset
0
AVODIS
disable ACVOUT
–
1
–
DL1ON
delay of YUVin
UVBINCON
UV sign of YUVin
UVFRM3
UV format of YUVin
UVFRM1
UV format of YUVin
YLEVEL
convert Y format
–
SELDLY
adjust delay of RGB/YUV-path
1
SELLIN
select soft mixer
0
CTRLDLY
delay control
0
FBLOFF
Fast Blank offset correction
31
FBLTEN
Fast Blank test
0
PASSRGB
soft mixer control
1
OVR
override value for PRIO-interface
–
PRIOID
set PRIO priority
–
PRIOEN
access to Picture Bus
1
LOAD
adjust load strength of
Picture Bus and PRIO bus
–
PUDIS
disable pull up
of YUV/RBG output
–
UVSW
UYUV output
–
BINO
oUV sign of
–
YUVO
soutput format
–
DTI
UV output format
–
IND
UV output format
–
MOD411ON
UV output format
–
CDEL
select UV output sample from 4:4:4
–
YDEL
adjust Y output delay
–
ADD16Q
black level
of Y output
–
DL422Y
additional
Y output delay
–
DL422C
additional
UV output delay
–
SYNCIN
UVof YUVin
–
SYNCOUT
of YUV output
–
SYNCSIM
H-syinput
–
D2KSYNC
syFSY-pin
–
–
AVINT
AVO control
–
PXSKWON
pixel skew corretion
–
P72BEN
72 bit data bypass
–
–
–
–
–
–
SECAM
delay for SECAM
FBLCLP
static Fast Blank
0
FBLDEL
delay Fast Blank vs. analog RGB/YUV
0
FSYINV
polarity FSY
AVOINV
polarity AVO
AVIINV
polarity AVI
–
NEGCLK
sclockedge
TESTLUY
test y channel
0
TESTCHU
test u channel
0
TESTCHV
test v channel
0
TESTFBL
test fbl channel
0
ICLPTST
test fbl clamp
0
PRIOSRC
Source for
PRIO request
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