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參數(shù)資料
| 型號： | CIP3250A |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費家電 |
| 英文描述： | Component Interface Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 16/44頁 |
| 文件大?。?/td> | 326K |
| 代理商： | CIP3250A |
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ADVANCE INFORMATION
CIP 3250A
16
Micronas
data on YUV bus must be kept dynamically for a half
clock cycle. Thus, capactitvie coupling from other sig-
nals to YUV bus must be avoided or reduced to a toler-
able minimum.
This procedure has many features which have an impact
on the appearance of a TV picture:
–
real-time bus arbitration (PIP, OSD, ...)
–
priorities are software configurable
–
different coefficients for different sources
2.16. I
2
C Serial Bus Control
Communication between the CIP 3250A and the exter-
nal controller is done via I
2
C bus. The CIP 3250A has an
I
2
C bus slave interface and uses I
2
C clock synchroniza-
tion to slow down the interface if required. The I
2
C bus
interface uses one level of subaddressing: one I
2
C bus
address is used to address the IC and a subaddress se-
lects one of the internal registers.
The registers of the CIP 3250A have 8 bit data size. All
registers are writeable (except subaddress hex27) and
readable as well. Register bits of parameter addresses,
which are marked with an X in the description field of the
register table, must be set to zero. All registers are initial-
ized to zero with reset.
Figure 2
–
12 shows I
2
C bus protocols for read and write
operations of the interface.
W
P
1 byte Data
W
S
S
Ack
Ack
Ack
Ack
0111 1100
0111 1100
R
S
Ack
SDA
SCL
1
0
S
P
P
1 byte Data
Ack
W
R
Ack
Nak
S
P
=
=
=
=
=
=
0
1
0
1
Start
Stop
Device Address = 110 1110[R/W]
Nak
Fig. 2–12:
I
2
C Bus Protocol
1101110
1101110
1101110
I
2
C write access
I
2
C read access
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