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參數(shù)資料
| 型號： | CH7009A-T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Chrontel CH7009 DVI / TV Output Device |
| 中文描述： | 昆泰CH7009和DVI / TV輸出設備 |
| 文件頁數(shù)： | 41/46頁 |
| 文件大?。?/td> | 580K |
| 代理商： | CH7009A-T |
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201-0000-035 Rev 1.1, 5/8/2000
41
CHRONTEL
Bit 2 of register TSTP is a test control, and should be left at the default value.
CH7009A
Bit 3 of register TSTP controls the datapath reset signal. A value of ‘0’ holds the datapath in a reset condition,
while a value of ‘1’, places the datapath in normal mode. The datapath is also reset at power on by an internally
generated power on reset signal.
Bit 4 of register TSTP controls the IIC reset signal. A value of ‘0’ holds the IIC registers in a reset condition, while
a value of ‘1’, places the IIC registers in normal mode. The IIC registers are also reset at power on by an internally
generated power on reset signal.
Power Management Register
Symbol:
Address:
Bits:
PM
49h
8
Register PM controls which circuitry within the CH7009 is operating, according to
Table 23
below.
Version ID Register
Symbol:
Address:
Bits:
VID
4Ah
8
Register VID is a read only register containing the version ID number of the CH7009. The MV default is ‘1’ when
the CH7009 is bonded out with Macrovision enabled, and ‘0’ when the CH7009 is bonded out with Macrovision
disabled.
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
DEFAULT:
DVIP
R/W
DVIL
R/W
TV DACPD3 DACPD2 DACPD1 DACPD0
R/W
R/W
R/W
0
0
FPD
R/W
R/W
R/W
0
0
0
0
0
1
Table 23: Power Management
Circuit Block
DVI PLL
DVI Encode, Serialize and
Is Operational When
DVIP = 1 & FPD = 0
DVIL = 1 & FPD = 0
Transmitter
VGA to TV Encoder
DAC 3
DAC 2
DAC 1
DAC 0
TV PLL, P-OUT and BCO pins
TV = 1 & FPD = 0
DACPD3 = 0 & FPD = 0
DACPD2 = 0 & FPD = 0
DACPD1 = 0 & FPD = 0
DACPD0 = 0 & FPD = 0
FPD = 0
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
DEFAULT:
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
R
R
0
R
0
R
0
R
0
R
0
R
0
R
0
MV
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