參數(shù)資料
型號： CH7009A-T
廠商： Electronic Theatre Controls, Inc.
英文描述： Chrontel CH7009 DVI / TV Output Device
中文描述： 昆泰CH7009和DVI / TV輸出設(shè)備
文件頁數(shù)： 36/46頁
文件大?。?/td> 580K
代理商： CH7009A-T
CHRONTEL
Input Data Format Register
CH7009A
IDF
1Fh
8
36
201-0000-035 Rev 1.1, 5/8/2000
Symbol:
Address:
Bits:
Bits 2-0 of register IDF select the input data format. See Input Interface on page 10 for a listing of available
formats.
Bit 3 of register IDF controls the horizontal sync polarity. A value of ‘0’ defines the horizontal sync to be active
low, and a value of ‘1’ defines the horizontal sync to be active high.
Bit 4 of register IDF controls the vertical sync polarity. A value of ‘0’ defines the vertical sync to be active low, and
a value of ‘1’ defines the vertical sync to be active high.
Bit 5 of register IDF controls the sync direction. A value of ‘0’ defines sync to be input to the CH7009, and a value
of ‘1’ defines sync to be output from the CH7009. The CH7009 can only output sync signals when operating as a
VGA to TV encoder, not when operating as a DVI transmitter.
Bit 6 of register IDF signifies when the CH7009 is to decode embedded sync signals present in the input data stream
instead of using the H and V pins. This feature is only available for input data format four. A value of ‘0’ selects the
H and V pins to be used as the sync inputs, and a value of ‘1’ selects the embedded sync signal.
Bit 7 of register IDF selects the input buffer used for the data, sync and clock input pins.
Connection Detect Register
Symbol:
Address:
Bits:
CD
20h
6
The Connection Detect Register provides a means to sense the connection of a TV to the four DAC outputs, and to
determine the status of the DVI hot plug detect pin. The status bits, DACT[3:0] correspond to the termination of the
four DAC outputs. However, the values contained in these STATUS BITS ARE NOT VALID until a sensing
procedure is performed. Use of this register requires a sequence of events to enable the sensing of outputs, then
reading out the applicable status bits. The detection sequence works as follows:
1) Set the power management register to enable all DAC’s.
2) Set the SENSE bit to a 1. This forces a constant output from the DAC’s. Note that during SENSE = 1, these 4
analog outputs are at steady state and no TV synchronization pulses are asserted.
3) Reset the SENSE bit to 0. This triggers a comparison between the voltage present on these analog outputs and
the reference value. During this step, each of the four status bits corresponding to individual DAC outputs will be
set if they are NOT CONNECTED.
4) Read the status bits. The status bits, DACT[3:0] now contain valid information which can be read to determine
which outputs are connected to a TV. Again, a “0” indicates a valid connection, a “1” indicates an unconnected
output.
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
DEFAULT:
IBS
R/W
DES
R/W
SYO
R/W
VSP
R/W
HSP
R/W
IDF2
R/W
IDF1
R/W
IDF0
R/W
0
0
0
0
0
0
0
0
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
DEFAULT:
HPIE2 Reserved
R/W
0
DVIT
DACT3
DACT2
DACT1
DACT0
SENSE
R/W
R/W
R
0
R
0
R
0
R
0
R
0
0
0
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