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參數(shù)資料
| 型號： | CH7303 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Chrontel CH7303 HDTV / DVI Encoder |
| 中文描述： | 昆泰CH7303的HDTV / DVI譯碼器 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大小： | 330K |
| 代理商： | CH7303 |
Chrontel
CH7303
Preliminary Advanced Information
209-0000-031
Rev. 0.4,
8/26/2002
1
Chrontel CH7303 HDTV / DVI Encoder
Features
Digital Visual Interface (DVI) Transmitter up to 165M
pixels/second
DVI low jitter PLL
DVI hot plug detection
Analog YPrPb outputs for HDTV
HDTV support for 480p, 576p, 720p, 1080i and 1080p
Macrovision
TM
copy protection support for HDTV
Programmable digital input interface supporting RGB
(15, 16, 24 or 30 bit) and YCrCb input data formats
Can output either RGB or YPrPb
TV / Monitor connection detect
Programmable power management
Three 10-bit video DAC outputs
Fully programmable through serial port
Complete Windows and DOS driver support
Low voltage interface support to graphics device
Offered in a 64-pin LQFP package
Backward pin compatible with CH7301 or CH7009/11
Support three additional 15 bit multiplexed RGB Input
Data Format (IDF 6,7.8)
Patent number 5,781,241
￥ Patent number 5,914,753
General Description
The CH7303 is a Display Controller device which accepts a
digital graphics input signal, and encodes and transmits data
through a DVI link (DFP can also be supported), VGA ports
(analog RGB) or a HDTV port (YPrPb). The device is able to
encode the video signals and generate synchronization signals
for analog HDTV interface standards and graphics standards
up to UXGA. The device accepts data over one 15-bit wide
variable voltage data port which supports 9 different data
formats including RGB and YCrCb.
The DVI processor includes a low jitter PLL for
generation of the high frequency serialized clock, and all
circuitry required to encode, serialize and transmit data.
The CH7303 is able to drive a DFP display at a pixel rate
of up to 165MHz, supporting UXGA resolution displays.
No scaling of input data is performed on the data output
to the DVI device.
In addition to DVI encoder modes, bypass modes are included
which perform color space conversion to HDTV standards
and generate and insert HDTV sync signals, or output VGA
style analog RGB for use as a CRT DAC.
Note: Other names and brands may be claimed as property by others.
SPC
SPD
GPIO[1:0]
RESET*
AS
HPDET
XCLK,XCLK*
ISET
MUX
2
Three
10-bit DAC's
DAC 2
DAC 1
DAC 0
Color Space
Conversion
Sync Decode
HDTV
YPbPr
RGB
DVI PLL
DVI Encode
DVI
Serialize
DVI Driver
TLC, TLC*
TDC0, TDC0*
TDC1, TDC1*
TDC2, TDC2*
Serial
Port
Control
Data
Latch,
Demux
Clock
Driver
/
30
/
2
H,V,DE
Latch
HSYNC,
VSYNC
DAC[1]
DAC[2]
DAC[0]
/
24
H,V
DE
2
/
2
/
2
/
2
/
2
/
2
D[14:0]
15
VREF
/
30
/
24
Figure 1: Functional Block Diagram
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