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參數(shù)資料
| 型號： | CH7303 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Chrontel CH7303 HDTV / DVI Encoder |
| 中文描述： | 昆泰CH7303的HDTV / DVI譯碼器 |
| 文件頁數(shù)： | 8/15頁 |
| 文件大?。?/td> | 330K |
| 代理商： | CH7303 |
CHRONTEL
CH7303
8
209-0000-031
Rev. 0.4,
8/26/2002
The input data format is shown in Figure 4 below. The Pixel Data bus represents a 15-bit, 12-bit or 8-bit multiplexed
data stream, which contains either RGB or YCrCb formatted data. The input data rate is 2X the pixel rate, and each pair
of Pn values (e.g.; P0a and P0b) will contain a complete pixel encoded as shown in Table 9 through Table 8.
It is assumed that the first clock cycle following the leading edge of the incoming horizontal sync signal contains the first
word (Pxa) of a pixel, if an active pixel was present immediately following the horizontal sync. This does not mean that
active data should immediately follow the horizontal sync, however. When the input is a YCrCb data stream the color-
difference data will be transmitted at half the data rate of the luminance data, with the sequence being set as Cb, Y, Cr,
Y, where Cb0,Y0,Cr0 refers to co-sited luminance and color-difference samples and the following Y1 byte refers to the
next luminance sample, per ITU-R BT.656 standards (the clock frequency is dependent upon the current mode, and is
not 27MHz as specified in ITU-R BT.656). All non-active pixels should be 0 in RGB formats, and 16 for Y, 128 for Cr
and Cb in YCrCb formats.
Dx[11:0]
Hx
XCLKx
(2X)
P1a
P0a
P2a
P1b
P0b
P2b
SAV
XCLKx
(1X)
DEx
Figure 4: 12-bit Multiplexed Input Data Formats (IDFx = 0,1,2,3,4)
Table 5: Multiplexed Input Data Formats (IDF = 0, 1)
IDF =
Format =
Pixel #
P0a
Bus Data
D[11]
G0[3]
D[10]
G0[2]
D[9]
G0[1]
D[8]
G0[0]
D[7]
B0[7]
D[6]
B0[6]
D[5]
B0[5]
D[4]
B0[4]
D[3]
B0[3]
D[2]
B0[2]
D[1]
B0[1]
D[0]
B0[0]
Table 6: Multiplexed Input Data Formats (IDF = 2, 3)
IDF =
Format =
Pixel #
P0a
Bus Data
D[11]
G0[4]
D[10]
G0[3]
D[9]
G0[2]
D[8]
B0[7]
D[7]
B0[6]
D[6]
B0[5]
D[5]
B0[4]
D[4]
B0[3]
0
12-bit RGB
P0b
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
R0[2]
R0[1]
R0[0]
G0[7]
G0[6]
G0[5]
G0[4]
1
12-bit RGB
P0b
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
G0[7]
G0[6]
G0[5]
R0[2]
R0[1]
R0[0]
G0[1]
P1a
G1[3]
G1[2]
G1[1]
G1[0]
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
P1b
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
G1[7]
G1[6]
G1[5]
G1[4]
P0a
G0[4]
G0[3]
G0[2]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
G0[0]
B0[2]
B0[1]
B0[0]
P1a
G1[4]
G1[3]
G1[2]
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
G1[0]
B1[2]
B1[1]
B1[0]
P1b
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
G1[7]
G1[6]
G1[5]
R1[2]
R1[1]
R1[0]
G1[1]
2
RGB 5-6-5
P0b
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
G0[7]
G0[6]
G0[5]
3
RGB 5-5-5
P0b
X
R0[7]
R0[6]
R0[5]
R0[4]
R0[3]
G0[7]
G0[6]
P1a
G1[4]
G1[3]
G1[2]
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
P1b
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
G1[7]
G1[6]
G1[5]
P0a
G0[5]
G0[4]
G0[3]
B0[7]
B0[6]
B0[5]
B0[4]
B0[3]
P1a
G1[5]
G1[4]
G1[3]
B1[7]
B1[6]
B1[5]
B1[4]
B1[3]
P1b
X
R1[7]
R1[6]
R1[5]
R1[4]
R1[3]
G1[7]
G1[6]
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