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參數(shù)資料
| 型號(hào)： | CH7009A-T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Chrontel CH7009 DVI / TV Output Device |
| 中文描述： | 昆泰CH7009和DVI / TV輸出設(shè)備 |
| 文件頁數(shù)： | 33/46頁 |
| 文件大?。?/td> | 580K |
| 代理商： | CH7009A-T |
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201-0000-035 Rev 1.1, 5/8/2000
33
CHRONTEL
CH7009A
CIV Control Register
Symbol:
Address:
Bits:
CIVC
10h
6
Bit 0 of register CIVC controls whether the FSCI value is used to set the sub-carrier frequency, or the automatically
calculated (CIV) value. When the CIVEN value is 1, the number calculated and present at the CIV registers will
automatically be used as the increment value for sub-carrier generation. Whenever this bit is set to 1, the CFRB bit
should be set to 0. It is recommended to use the FSCI registers, and not the CIVEN mode for Macrovision
applications
Bit 1 of register CIVC forces the CIV algorithm to generate the PAL-N (Argentina) sub-carrier frequency when it is
set to ‘1’. When this bit is set to ‘0’, the VOS[1:0] value is used by the CIV algorithm to determine which sub-
carrier frequency to generate.
Bits 3-2 of register CIVC control the hysteresis circuit which is used to calculate the CIV value. The default value
should be used.
Bits 5-4 of register CIVC contain the MSB values for the calculated increment value (CIV) readout. This is
described in detail in the CIV register description.
Table 18: FSCI Values (625-Line TV-Out Modes)
Mode
PAL
“Normal Dot Crawl”
806,021,060
644,816,848
601,829,058
470,178,951
677,057,690
537,347,373
806,021,060
644,816,848
537,347,373
690,875,194
564,214,742
483,612,636
645,499,916
528,951,320
453,386,846
621,787,675
544,064,215
483,612,636
705,268,427
PAL-N
“Normal Dot Crawl”
651,209,077
520,967,262
486,236,111
379,871,962
547,015,625
434,139,385
651,209,077
520,967,262
434,139,385
558,179,209
455,846,354
390,725,446
521,519,134
427,355,957
366,305,106
502,361,288
439,566,127
390,725,446
569,807,942
0
1
4
5
8
9
13
14
15
22
23
24
25
26
27
31
32
33
37
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
DEFAULT:
CIV25
R/W
CIV24
R/W
CIVC1
R/W
CIVC0
R/W
PALN
R/W
CIVEN
R/W
0
0
0
0
0
1
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