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參數資料
| 型號： | CH7009A-T |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Chrontel CH7009 DVI / TV Output Device |
| 中文描述： | 昆泰CH7009和DVI / TV輸出設備 |
| 文件頁數： | 34/46頁 |
| 文件大小： | 580K |
| 代理商： | CH7009A-T |
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CHRONTEL
Calculated Increment Value Register
CH7009A
CIV
11h –
13h
8 each
34
201-0000-035 Rev 1.1, 5/8/2000
Symbol:
Address:
Bits:
Registers CIV contain the value that was calculated by the CH7009 as the sub-carrier increment value. The entire
bit field, CIV[25:0], is comprised of these three registers plus the MSB values contained in the CIV Control register,
bits CIV25 and CIV24. This value is used when the CIVEN bit is set to ‘1’. The bit locations are specified below.
Register Contents
10hCIV[25:24]
11hCIV[23:16]
12hCIV[15:8]
13hCIV[7:0]
Clock Mode Register
Symbol:
Address:
Bits:
CM
1Ch
4
Bit 0 of register CM signifies the XCLK frequency. A value of ‘0’ is used when the XCLK is at the pixel frequency
(duel edge clocking mode) and a value of ‘1’ is used when the XCLK is twice the pixel frequency (single edge
clocking mode).
Bit 1 of register CM controls the P-OUT clock frequency. A value of ‘0’ generates a clock output at the pixel
frequency, while a value of ‘1’ generates a clock at twice the pixel frequency.
Bit 2 of register CM controls the phase of the XCLK clock input to the CH7009. A value of ‘1’ inverts the XCLK
signal at the input of the device. This control is used to select which edge of the XCLK signal to use for latching
input data.
Bit 3 of register CM controls whether the device operates in master or slave clock mode. In master mode (M/S* =
‘1’), the 14.31818MHz clock is used as a frequency reference in the TV PLL, and the M and N values are used to
determine the TV PLL’s operating frequency. In slave mode (M/S* = ‘0’) the XCLK input is used as a reference to
the TV PLL. The M and N TV PLL divider values are forced to one.
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
DEFAULT:
CIV#
R/W
CIV#
R/W
CIV#
R/W
CIV#
R/W
CIV#
R/W
CIV#
R/W
CIV#
R/W
CIV#
R/W
0
0
0
0
0
0
0
0
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
DEFAULT:
M/S*
R/W
MCP
R/W
PCM
R/W
XCM
R/W
0
0
0
0
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