參數(shù)資料
型號(hào)： CH7009A-T
廠商： Electronic Theatre Controls, Inc.
英文描述： Chrontel CH7009 DVI / TV Output Device
中文描述： 昆泰CH7009和DVI / TV輸出設(shè)備
文件頁數(shù)： 38/46頁
文件大?。?/td> 580K
代理商： CH7009A-T
CHRONTEL
Buffered Clock Output Register
CH7009A
BCO
22h
8
38
201-0000-035 Rev 1.1, 5/8/2000
Symbol:
Address:
Bits:
Bits 2-0 of register BCO select the signal output at the BCO pin, according to
Table 20
below:
Bit 3 of register BCO selects the polarity of the BCO output. A value of ‘1’ does not invert the signal at the output
pad.
Bit 4 of register BCO enables the BCO output. When BCOEN is high, the BCO pin will output the selected signal.
When BCOEN is low, the BCO pin will be held in tri-state mode.
Bits 7-5 of register BCO select the K3 divider, according to
Table 21
below.
DVI Control Input Register
Symbol:
Address:
Bits:
TCTL
31h
8
Bits 3-0 of register TCTL set the DVI control inputs applied to the green and red channels during sync intervals. It
is recommended to leave these controls at the default value.
Bits 7-4 of register TCTL control the DVI PLL phase detector. The default value is recommended.
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
DEFAULT:
SHF2
R/W
SHF1
R/W
SHF0
R/W
BCOEN
R/W
BCOP
R/W
BCO2
R/W
BCO1
R/W
BCO0
R/W
0
0
0
0
0
0
0
0
Table 20: BCO Output Signal
BCO[2:0]
Buffered Clock Output
000
The 14MHz crystal
001
(for test use only)
010
VCO divided by K3
011
Field ID
BCO[2:0]
100
101
110
111
Buffered Clock Output
(for test use only)
(for test use only)
VGA Vertical Sync
TV Vertical Sync
Table 21: K3 Selection
SHF[2:0]
000
001
010
011
100
101
110
111
K3
2.5
3.0
3.5
4.0
4.5
5.0
6.0
7.0
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
DEFAULT:
TPPD3
R/W
TPPD 2
R/W
TPPD 1
R/W
TPPD 0
R/W
CTL3
R/W
CTL2
R/W
CTL1
R/W
CTL0
R/W
1
0
0
0
0
0
0
0
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