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參數(shù)資料
| 型號： | C9810AYB |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 332K |
| 代理商： | C9810AYB |
+/+
…when timing is critical
C9810
Low EMI Clock Generator for Intel
810 Chipset for Mobile Applications
Advanced Information
IMI Confidential
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev 0.4
8/31/1999
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
Page 3 of 15
http://www.imicorp.com
Test Mode Function
Test Mode Functionality
SEL2
SEL1
SEL0
CPU
SDRAM
3V66
PCI
48 MHz
REF
IOAPIC
x
0
1
TCLK÷2
TCLK÷3
TCLK÷6
TCLK÷2
TCLK
TCLK÷6
Table 2
Note: TCLK is a test clock over driven on the XIN input during test mode.
Power Management Functions
Power Management on this device is controlled by a single pin, PD# (pin32). When PD# is high (default) the device is in
running and all signals are active.
When PD# is asserted (forced) low, the device is in shutdown (or in power down) mode and all power supplies (3.3V and
2.5V except for VDDA/pin 27) may be removed. When in power down, all outputs are synchronously stopped in a low
state (see Fig.2 below), all PLL’s are shut off, and the crystal oscillator is disabled. When the device is shutdown the IC
function is also disabled.
Power Management Timing
100MHz
PCI
33MHz
SDRAM
CLOCK
33MHz
Undefined
CPU
66MHz
30nS
0nS
IOAPIC
3V66
100MHz
20nS
10nS
40nS
50nS
PWRDN#
REF
USB
14.3MHz
48MHz
Undefined
Fig.2
Power Management Current
PD#, SEL[2..0]
(CPU Clock)
Maximum 2.5 Volt Current
Consumption (VDD2.5 =2.625)
Maximum 3.3 Volt Current Consumption
(VDD3.3 = 3.465 V)
0XXX (Power down)
100 A
200 A
1010 (66MHz)
70 mA
280 mA
1011 (100MHz)
100 mA
280 mA
111X (133MHz)
133 mA
280 mA
Table 3
When exiting the power down mode, the designer must supply power to the VDD pins first, a minimum of 200mS before
releasing the PD# pin high.
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