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參數(shù)資料
| 型號(hào)： | C9810AYB |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 332K |
| 代理商： | C9810AYB |
+/+
…when timing is critical
C9810
Low EMI Clock Generator for Intel
810 Chipset for Mobile Applications
Advanced Information
IMI Confidential
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev 0.4
8/31/1999
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
Page 5 of 15
http://www.imicorp.com
Power on Bi-Directional Pins
Power Up Condition:
Pin 48 (REL2/REF) is a Power up bi-directional pin and is used for selecting the host frequency in page 1, table 1.
During power-up of the device, this pin is in input mode (see Fig 4, below), therefore; it is considered input select pins
internal to the IC. After a settling time, the selection data is latch into the internal control register and this pin becomes a
clock output.
-
Hi-Z INPUTS
TOGGLE OUTPUTS
POWER SUPPLY
RAMP
SELECT DATA IS LATCHED INTO REGISTER THEN PIN BECOMES A REF CLOCK OUTPUT SIGNAL
REF / SEL2
(Pin 1)
VDD RAIL
Strapping Resistor Options:
The power up bi-directional pins have a large value pull-
up each (250K
), therefore, a selection “1” is the
default. If the system uses a slow power supply (over
5mS settling time), then it is recommended to use an
external Pull-up (Rup) in order to insure a high
selection. In this case, the designer may choose one of
two configurations, see Fig.5A and B.
Fig. 5A represents an additional pull up resistor 50K
connected from the pin to the power line, which allows a
faster pull to a high level.
If a selection “0” is desired, then a jumper is placed on
JP1 to a 5K
resistor as implemented as shown in
Fig.5A. Please note the selection resistors (Rup and
Rdn
) are placed before the Damping resistor (Rd)
close to the pin.
Fig. 5B represent a single resistor 10K
connected to a
3-way jumper, JP2. When a “1” selection is desired, a
jumper is placed between leads1 and 3. When a “0”
selection is desired, a jumper is placed between leads 1
and 2.
Load
F ig. 5A
F ig. 5B
Vd d
Ru p
10K
Rd
IM I C 9810
B idire c tional
JP 1
J U MPER
JP 2
3 W a y J u m per
Rs e l
10K
Rd
IM I C 9810
B idire c tional
Rd n
10K
S ee D e s c rip tion
1
2
3
Fig.4
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