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參數(shù)資料
| 型號： | C9810AYB |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 332K |
| 代理商： | C9810AYB |
+/+
…when timing is critical
C9810
Low EMI Clock Generator for Intel
810 Chipset for Mobile Applications
Advanced Information
IMI Confidential
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev 0.4
8/31/1999
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
Page 7 of 15
http://www.imicorp.com
Serial Control Registers
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only on true power up.
In write mode, following the acknowledge of the Address Byte (D2), two additional bytes must be sent:
1) “Command Code“ byte, and
2) “Byte Count” byte.
Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged.
After the Command Code and the Count bytes have been acknowledged, the sequence (Byte 0, Byte 1, and Byte2)
described in Fig7 will be valid and acknowledged.
In the Read Mode (See Fig7B, p.8), the clock gen. acknowledges Address D3, and immediately transmits data starting
with Byte count, then Byte 0, 1, 2, ... After each transmitted byte, this device waits for an acknowledge before
transmitting the next byte.
Byte 0: CPU Clock Register (1=Enable, 0=Disable, Default=07)
Bit
@Pup
Pin#
Description
70
-
Reserved
60
-
Reserved
50
-
Reserved
40
-
Reserved
3
0
-
Spread Spectrum
21
24
DOT
11
23
USB
0
1
41
CPU2
Byte 1: SDRAM Clock Register (1=Enable, 0=Disable, Default=EC)
Bit
@Pup
Pin#
Description
7
1
32
SDRAM3
6
1
33
SDRAM2
5
1
35
DCLK
40
-
Reserved
3
1
37
SDRAM1
2
1
38
SDRAM0
10
-
Reserved
00
-
Reserved
Byte 2: PCI Clock Register (1=Enable, 0=Disable, Default=FE)
Bit
@Pup
Pin#
Description
71
18
PCI6
61
17
PCI5
51
15
PCI4
41
14
PCI3
31
12
PCI2
21
11
PCI1
11
10
PCI0
00
-
Reserved
Byte 3: Reserved Register (Default=00)
Byte 4: Reserved Register (Default=00)
Byte 5: SSCG Control Register (Default=00)
Bit
@Pup
Description
7
0
Spread Spectrum Mode (0=down,
1=center)
6
0
Ref. Table 4
5
0
Ref. Table 4
40
Reserved
30
Reserved
20
Reserved
10
Reserved
00
Reserved
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