參數(shù)資料
型號(hào)： C9810AYB
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： SSOP-48
文件頁(yè)數(shù)： 8/15頁(yè)
文件大小： 332K
代理商： C9810AYB
+/+
…when timing is critical
C9810
Low EMI Clock Generator for Intel
810 Chipset for Mobile Applications
Advanced Information
IMI Confidential
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev 0.4
8/31/1999
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
Page 2 of 15
http://www.imicorp.com
Pin Description
PIN No.
Pin Name
PWR
I/O
TYPE
Description
48
SEL2/REF
VDD
I/O
3.3V 14.318 MHz clock output. This Is a power on bi-directional
pin. During power up, this pin is an input “SEL2” for setting the
CPU frequency (see table1, page 1) (see app not, page 5).
When the power reaches the rail, this pin becomes a buffered
output of the signal applied at Xin (typically 14.318 MHz).
2
XIN
VDD
I
OSC1
14.318MHz Crystal input
3
XOUT
VDD
O
14.318MHz Crystal output
10, 11, 12,
14, 15, 17,
18
PCI(0:6)
VDD
O
3.3V PCI clock outputs. Synchronous to CPU clock. See fig. 3,
page 4.
6, 7
3V66(0:1)
VDD
O
3.3V Fixed 66.6 MHz clock outputs
23
USB
VDD
O
3.3V Fixed 48 MHz clock outputs
24
DOT
VDD
O
3.3V Fixed 48 MHz clock outputs
26, 27
SEL(0,1)
VDD
I
3.3V LVTTL compatible inputs for logic selection. Each input
has an internal pull-up (Typ. 250K
)
28
SDATA
VDD
I
IC compatible SDATA input. Has an internal pull-up (>100K
)
29
SCLK
VDD
I
IC compatible SCLK input. Has an internal pull-up (>100K
)
30
PWR_DWN#
VDD
I
3.3V LVTTL compatible input. Device enters powerdown mode
When held LOW. Has an internal pull-up (typically 250 k).
38, 37, 32,
33, 35
SDRAM(0:3)
DCLK
VDDS
O
3.3V SDRAM clock outputs. See table1, page 1 for frequency
table.
42, 41
CPU(1:2)
VDDC
O
2.5V Host bus clock outputs. See table 1, page 1 for frequency
selection.
46, 45
IOAPIC(0,1)
VDDI
O
2.5V clock IOAPIC outputs. They are synchronous to CPU
clock and fixed at 33.3 MHz. See figure 3, page 4.
1
VDD
-
3.3V Power Supply
20
VDDA
-
Analog circuitry 3.3V Power Supply
21
VSSA
-
Analog circuitry Ground.
43
VDDC
-
2.5V Power Supply’s for CPU (1:2) clock outputs.
4
VSS
-
Common Ground pin.
39, 34
VDDS
-
3.3V power support for SDRAM clock output.
40
VSSC
Ground pin for CPU (1:2) clock outputs.
31, 36
VSSS
Ground pins for SDRAM and DCLK clock outputs.
25
VDD48
3.3V power supply for 48 MHz (0:1) clock outputs.
22
VSS48
Ground return for 48 MHz (0:1) clock outputs.
9, 19
VDDP
3.3V power supply for PCI (0:6) clock outputs.
16, 13
VSSP
Ground return for PCI (0:6) clock outputs.
8
VDD66
3.3V power supply for 3V66 (0:1) output clocks
5
VSS66
Ground return for 3V66 (0:1) clock outputs.
44
VDDI
-
2.5V power supply for IOAPIC (0:1) clock outputs.
47
VSSI
-
Ground return for IOAPIC (0:1) clock outputs.
A bypass capacitor (0.1
F) should be placed as close as possible to each positive power pin. If these bypass capacitors
are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
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