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參數(shù)資料
| 型號： | C9810AYB |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 332K |
| 代理商： | C9810AYB |
+/+
…when timing is critical
C9810
Low EMI Clock Generator for Intel
810 Chipset for Mobile Applications
Advanced Information
IMI Confidential
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev 0.4
8/31/1999
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
Page 6 of 15
http://www.imicorp.com
2-Wire I
2C Control Interface
The 2-wire control interface implements a read/write interface according to Philips IC specification. (See Fig. 7 / P. 8).
The device can be read back by using standard I
2C command bytes. Sub addressing is not supported, thus all preceding
bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows each clock output to
be individually enabled or disabled. 100 Kbits/second (standard mode) data transfer is supported.
During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK
is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the
start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a transfer
cycle is an 8-bit address. W#=0 in write mode.
The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on
the SDATA wire following reception of each byte. Data is transferred MSB first at a max rate of 100kbits/S. The device
will not respond to any other control interface conditions, and previously set control registers are retained.
I
2C Test Circuitry
Fig.6
Note: Buffer is 7407 with VCC @ 5.0 V
2.2 K
Device under Test
SDATA
DATAIN
SCLK
DATAOUT
CLOCK
+ 5V
2.2 K
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