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參數(shù)資料
| 型號(hào)： | C9810AYB |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 332K |
| 代理商： | C9810AYB |
+/+
…when timing is critical
C9810
Low EMI Clock Generator for Intel
810 Chipset for Mobile Applications
Advanced Information
IMI Confidential
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev 0.4
8/31/1999
MILPITAS, CA 95035, USA TEL: 408-263-6300, FAX 408-263-6571
Page 10 of 15
http://www.imicorp.com
Maximum Ratings
Maximum Input Voltage Relative to VSS:
VSS - 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
-65C to + 150C
Operating Temperature:
0C to +85C
Maximum ESD protection
2KV
Maximum Power Supply:
5.5V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Parameters (all outputs loaded per table 5 below)
Characteristic
Symbol
Min
Typ
Max
Units
Conditions
Input Low Voltage
VIL1
-
1.0
Vdc
Input High Voltage
VIH1
2.0
-
Vdc
Note 1
Input Low Voltage
VIL2
-
1.0
Vdc
Input High Voltage
VIH2
2.2
-
Vdc
Note 2
Input Low Current (@VIL = VSS)
IIL
-66
-5
A
Input High Current (@VIL =VDD)
IIH
5
A
For internal Pull up resistors,
Notes 1,3
Tri-State leakage Current
Ioz
-
10
A
Dynamic Supply Current
Idd3.3V
-
280
mA
Sel2 = Sel1 = Sel0 = 1
Dynamic Supply Current
Idd2.5V
-
100
mA
Sel2 = Sel1 = Sel0 = 1
Static Supply Current
Isdd
-
300
A
Sel2 = Sel1 = Sel0 = x
Input pin capacitance
Cin
-
5
pF
Output pin capacitance
Cout
-
6
pF
Pin capacitance
Lpin
-
7
nH
Crystal pin capacitance
Cxtal
32
36
38
pF
Measured from Pin to Ground. Note 4
Crystal DC Bias Voltage
VBIAS
0.3Vdd
Vdd/2
0.7Vdd
V
Crystal Startup time
Txs
-
40
S
From Stable 3.3V power supply.
VDD=VDDS = 3.3V
±5%, VDDC = VDDI = 2.5 ± 5%, TA = 0 to +70C
Note1:
Applicable to input signals: Sel(0:1), PD#
Note2:
Applicable to Sdata, and Sclk.
Note3:
Although internal pull-up resistors have a typical value of 250K, this value may vary between 200K and 500K.
Note4:
Although the device will reliably interface with crystals of a 17pF – 20pF CL range, it is optimized to interface with a typical CL = 18pF
crystal specifications.
Clock Name
Max Load (in pF)
CPU, IOAPIC, REF, USB
20
PCI, SDRAM, 3V66
30
DOT
15
Table 5
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