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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� C8051F005DK
寤犲晢锛� Silicon Laboratories Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 24/171闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� DEV KIT FOR F005/006/007
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 1
椤�(l猫i)鍨嬶細 MCU
閬╃敤浜庣浉闂�(gu膩n)鐢�(ch菐n)鍝侊細 Silicon Laboratories C8051 F005/006/007
鎵€鍚墿鍝侊細 瑭�(p铆ng)浼版澘锛岄浕婧�锛孶SB 绶氱簻锛岄仼閰嶅櫒鍜屾枃妾�
鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 626 (CN2011-ZH PDF)
鐩搁棞(gu膩n)鐢�(ch菐n)鍝侊細 C8051F007-GQR-ND - IC 8051 MCU 32K FLASH 32LQFP
C8051F006-GQR-ND - IC 8051 MCU 32K FLASH 48TQFP
C8051F005-GQR-ND - IC 8051 MCU 32K FLASH 64TQFP TAP
336-1190-ND - IC 8051 MCU 32K FLASH 32LQFP
336-1189-ND - IC 8051 MCU 32K FLASH 48TQFP
336-1187-ND - IC 8051 MCU 32K FLASH 64TQFP
鍏跺畠鍚嶇ū(ch膿ng)锛� 336-1188
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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
1.1.
CIP-51
TM CPU
1.1.1.
Fully 8051 Compatible
The C8051F000 family utilizes Silicon Laboratories鈥� proprietary CIP-51 microcontroller core. The CIP-51 is fully
compatible with the MCS-51
TM instruction set. Standard 803x/805x assemblers and compilers can be used to
develop software.
The core has all the peripherals included with a standard 8052, including four 16-bit
counter/timers, a full-duplex UART, 256 bytes of internal RAM space, 128 byte Special Function Register (SFR)
address space, and four byte-wide I/O Ports.
1.1.2.
Improved Throughput
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the standard 8051
architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to
execute with a maximum system clock of 12-to-24MHz.
By contrast, the CIP-51 core executes 70% of its
instructions in one or two system clock cycles, with only four instructions taking more than four system clock
cycles.
The CIP-51 has a total of 109 instructions. The number of instructions versus the system clock cycles to execute
them is as follows:
Instructions
26
50
5
14
7
3
1
2
1
Clocks to Execute
1
2
2/3
3
3/4
4
4/5
5
8
With the CIP-51鈥檚 maximum system clock at 25MHz, it has a peak throughput of 25MIPS. Figure 1.4 shows a
comparison of peak throughputs of various 8-bit microcontroller cores with their maximum system clocks.
Figure 1.4. Comparison of Peak MCU Execution Speeds
5
10
15
20
ADuC812
8051
(16MHz
clk)
Philips
80C51
(33MHz
clk)
Microchip
PIC17C75x
(33MHz
clk)
Silicon Labs
CIP-51
(25MHz clk)
MIPS
25
Rev. 1.7
12
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
LM4040C25QDBZTG4 IC VREF SHUNT PREC 2.5V SOT-23-3
LB2016T330K INDUCTOR WOUND 33UH 85MA 0806
GEM12DTMN-S189 CONN EDGECARD 24POS R/A .156 SLD
LM4040C25IDBZTG4 IC VREF SHUNT PREC 2.5V SOT-23-3
GEM12DTMH-S189 CONN EDGECARD 24POS R/A .156 SLD
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鍙冩暩(sh霉)鎻忚堪
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C8051F005DK-E 鍔熻兘鎻忚堪:DEV KIT FOR C8051F005/F006/F007 RoHS:鍚� 椤�(l猫i)鍒�:绶ㄧ▼鍣�锛岄枊(k膩i)鐧�(f膩)绯荤当(t菕ng) >> 閬�(gu貌)鏅�(sh铆)/鍋滅敘(ch菐n)闆朵欢绶ㄨ櫉(h脿o) 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- 椤�(l猫i)鍨�:MCU 閬╃敤浜庣浉闂�(gu膩n)鐢�(ch菐n)鍝�:Freescale MC68HC908LJ/LK锛�80-QFP ZIF 鎻掑彛锛� 鎵€鍚墿鍝�:闈㈡澘銆佺簻绶�銆佽粺浠�銆佹暩(sh霉)鎿�(j霉)琛ㄥ拰鐢ㄦ埗鎵嬪唺(c猫) 鍏跺畠鍚嶇ū(ch膿ng):520-1035
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