參數(shù)資料
型號(hào): C8051F005DK
廠商: Silicon Laboratories Inc
文件頁數(shù): 17/171頁
文件大?。?/td> 0K
描述: DEV KIT FOR F005/006/007
標(biāo)準(zhǔn)包裝: 1
類型: MCU
適用于相關(guān)產(chǎn)品: Silicon Laboratories C8051 F005/006/007
所含物品: 評(píng)估板,電源,USB 線纜,適配器和文檔
產(chǎn)品目錄頁面: 626 (CN2011-ZH PDF)
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其它名稱: 336-1188
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
16. SMBus / I2C Bus
The SMBus serial I/O interface is compliant with the System Management Bus Specification, version 1.1. It is a
two-wire, bi-directional serial bus, which is also compatible with the I
2C serial bus. Reads and writes to the
interface by the system controller are byte oriented with the SMBus interface autonomously controlling the serial
transfer of the data. Data can be transferred at up to 1/8
th of the system clock if desired (this can be faster than
allowed by the SMBus specification, depending on the system clock used). A method of extending the clock-low
duration is used to accommodate devices with different speed capabilities on the same bus.
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver, and
data transfers from an addressed slave transmitter to a master receiver. The master device initiates both types of
data transfers and provides the serial clock pulses. The SMBus interface may operate as a master or a slave.
Multiple master devices on the same bus are also supported. If two or more masters attempt to initiate a data
transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitration.
Figure 16.1. SMBus Block Diagram
SFR Bus
Data Path
Control
SFR Bus
Write to
SMB0DAT
SMBUS CONTROL LOGIC
Read
SMB0DAT
SMB0ADR
S
L
V
6
G
C
S
L
V
5
S
L
V
4
S
L
V
3
S
L
V
2
S
L
V
1
S
L
V
0
C
R
O
S
B
A
R
Clock Divide
Logic
SYSCLK
SMB0CR
C
R
7
C
R
6
C
R
5
C
R
4
C
R
3
C
R
2
C
R
1
C
R
0
SCL
FILTER
N
SDA
Control
0000000b
7 MSBs
8
A
B
A=B
8
0
1
2
3
4
5
6
7
SMB0DAT
8
SMB0CN
S
T
A
S
I
A
F
T
E
T
O
E
N
S
M
B
U
S
Y
S
T
O
SMB0STA
S
T
A
4
S
T
A
3
S
T
A
2
S
T
A
1
S
T
A
0
SCL
Control
Status Generation
Arbitration
SCL Synchronization
SCL Generation (Master Mode)
IRQ Generation
S
T
A
5
S
T
A
6
S
T
A
7
A
B
A=B
SMBUS
IRQ
Interrupt
Request
Port I/O
1
0
SDA
FILTER
N
7
113
Rev. 1.7
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C8051F005DK-A 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類別:編程器,開發(fā)系統(tǒng) >> 過時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK(80-QFP ZIF 插口) 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊(cè) 其它名稱:520-1035
C8051F005DK-B 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類別:編程器,開發(fā)系統(tǒng) >> 過時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK(80-QFP ZIF 插口) 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊(cè) 其它名稱:520-1035
C8051F005DK-E 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類別:編程器,開發(fā)系統(tǒng) >> 過時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK(80-QFP ZIF 插口) 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊(cè) 其它名稱:520-1035
C8051F005DK-H 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類別:編程器,開發(fā)系統(tǒng) >> 過時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK(80-QFP ZIF 插口) 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊(cè) 其它名稱:520-1035
C8051F005DK-J 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類別:編程器,開發(fā)系統(tǒng) >> 過時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK(80-QFP ZIF 插口) 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊(cè) 其它名稱:520-1035