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參數(shù)資料
| 型號(hào)： | C8051F005DK |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 108/171頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | DEV KIT FOR F005/006/007 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類(lèi)型： | MCU |
| 適用于相關(guān)產(chǎn)品： | Silicon Laboratories C8051 F005/006/007 |
| 所含物品： | 評(píng)估板，電源，USB 線(xiàn)纜，適配器和文檔 |
| 產(chǎn)品目錄頁(yè)面： | 626 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | C8051F007-GQR-ND - IC 8051 MCU 32K FLASH 32LQFP C8051F006-GQR-ND - IC 8051 MCU 32K FLASH 48TQFP C8051F005-GQR-ND - IC 8051 MCU 32K FLASH 64TQFP TAP 336-1190-ND - IC 8051 MCU 32K FLASH 32LQFP 336-1189-ND - IC 8051 MCU 32K FLASH 48TQFP 336-1187-ND - IC 8051 MCU 32K FLASH 64TQFP |
| 其它名稱(chēng)： | 336-1188 |
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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
6.2.
ADC Modes of Operation
The ADC uses VREF to determine its full-scale voltage, thus the reference must be properly configured before
performing a conversion (see Section 9). The ADC has a maximum conversion speed of 100ksps. The ADC
conversion clock is derived from the system clock. Conversion clock speed can be reduced by a factor of 2, 4, 8 or
16 via the ADCSC bits in the ADC0CF Register. This is useful to adjust conversion speed to accommodate
different system clock speeds.
A conversion can be initiated in one of four ways, depending on the programmed states of the ADC Start of
Conversion Mode bits (ADSTM1, ADSTM0) in ADC0CN. Conversions may be initiated by:
1.
Writing a 1 to the ADBUSY bit of ADC0CN;
2.
A Timer 3 overflow (i.e. timed continuous conversions);
3.
A rising edge detected on the external ADC convert start signal, CNVSTR;
4.
A Timer 2 overflow (i.e. timed continuous conversions).
Writing a 1 to ADBUSY provides software control of the ADC whereby conversions are performed “on-demand”.
During conversion, the ADBUSY bit is set to 1 and restored to 0 when conversion is complete. The falling edge of
ADBUSY triggers an interrupt (when enabled) and sets the ADCINT interrupt flag. Note: When conversions are
performed “on-demand”, the ADCINT flag, not ADBUSY, should be polled to determine when the
conversion has completed. Converted data is available in the ADC data word MSB and LSB registers, ADC0H,
ADC0L. Converted data can be either left or right justified in the ADC0H:ADC0L register pair (see example in
Figure 6.9) depending on the programmed state of the ADLJST bit in the ADC0CN register.
The ADCTM bit in register ADC0CN controls the ADC track-and-hold mode. In its default state, the ADC input is
continuously tracked, except when a conversion is in progress. Setting ADCTM to 1 allows one of four different
low power track-and-hold modes to be specified by states of the ADSTM1-0 bits (also in ADC0CN):
1.
Tracking begins with a write of 1 to ADBUSY and lasts for 3 SAR clocks;
2.
Tracking starts with an overflow of Timer 3 and lasts for 3 SAR clocks;
3.
Tracking is active only when the CNVSTR input is low;
4.
Tracking starts with an overflow of Timer 2 and lasts for 3 SAR clocks.
Modes 1, 2 and 4 (above) are useful when the start of conversion is triggered with a software command or when the
ADC is operated continuously. Mode 3 is used when the start of conversion is triggered by external hardware. In
this case, the track-and-hold is in its low power mode at times when the CNVSTR input is high. Tracking can also
be disabled (shutdown) when the entire chip is in low power standby or sleep modes.
Figure 6.2. 10-Bit ADC Track and Conversion Example Timing
12
345
678
9
10 11 12 13 14 15 16
CNVSTR
(ADSTM[1:0]=10)
ADCTM=1
Track
Convert
Low Power Mode
ADCTM=0
Track Or Convert
Convert
Track
Low Power or
Convert
Timer2, Timer3 Overflow;
Write 1 to ADBUSY
(ADSTM[1:0]=00, 01, 11)
ADCTM=1
Track
Convert
Low Power Mode
ADCTM=0
Track or Convert
Convert
Track
Low Power or
Convert
A. ADC Timing for External Trigger Source
B. ADC Timing for Internal Trigger Sources
SAR Clocks
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
SAR Clocks
41
Rev. 1.7
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| C8051F005DK-A | 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 過(guò)時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、纜線(xiàn)、軟件、數(shù)據(jù)表和用戶(hù)手冊(cè) 其它名稱(chēng):520-1035 |
| C8051F005DK-B | 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 過(guò)時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、纜線(xiàn)、軟件、數(shù)據(jù)表和用戶(hù)手冊(cè) 其它名稱(chēng):520-1035 |
| C8051F005DK-E | 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 過(guò)時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、纜線(xiàn)、軟件、數(shù)據(jù)表和用戶(hù)手冊(cè) 其它名稱(chēng):520-1035 |
| C8051F005DK-H | 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 過(guò)時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、纜線(xiàn)、軟件、數(shù)據(jù)表和用戶(hù)手冊(cè) 其它名稱(chēng):520-1035 |
| C8051F005DK-J | 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 過(guò)時(shí)/停產(chǎn)零件編號(hào) 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類(lèi)型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK（80-QFP ZIF 插口） 所含物品:面板、纜線(xiàn)、軟件、數(shù)據(jù)表和用戶(hù)手冊(cè) 其它名稱(chēng):520-1035 |
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