參數(shù)資料
型號: C8051F005DK
廠商: Silicon Laboratories Inc
文件頁數(shù): 166/171頁
文件大?。?/td> 0K
描述: DEV KIT FOR F005/006/007
標(biāo)準(zhǔn)包裝: 1
類型: MCU
適用于相關(guān)產(chǎn)品: Silicon Laboratories C8051 F005/006/007
所含物品: 評估板,電源,USB 線纜,適配器和文檔
產(chǎn)品目錄頁面: 626 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: C8051F007-GQR-ND - IC 8051 MCU 32K FLASH 32LQFP
C8051F006-GQR-ND - IC 8051 MCU 32K FLASH 48TQFP
C8051F005-GQR-ND - IC 8051 MCU 32K FLASH 64TQFP TAP
336-1190-ND - IC 8051 MCU 32K FLASH 32LQFP
336-1189-ND - IC 8051 MCU 32K FLASH 48TQFP
336-1187-ND - IC 8051 MCU 32K FLASH 64TQFP
其它名稱: 336-1188
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
13.1.
Power-on Reset
The C8051F000 family incorporates a power supply monitor that holds the MCU in the reset state until VDD rises
above the VRST level during power-up. (See Figure 13.2 for timing diagram, and refer to Table 13.1 for the
Electrical Characteristics of the power supply monitor circuit.) The /RST pin is asserted (low) until the end of the
100ms VDD Monitor timeout in order to allow the VDD supply to become stable.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other reset
flags in the RSTSRC Register are indeterminate. PORSF is cleared by a reset from any other source. Since all
resets cause program execution to begin at the same location (0x0000), software can read the PORSF flag to
determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be
undefined after a power-on reset.
13.2.
Software Forced Reset
Writing a 1 to the PORSF bit forces a Power-On Reset as described in Section 13.1.
Figure 13.2. VDD Monitor Timing Diagram
/RST
t
vol
ts
1.0
2.0
Logic HIGH
Logic LOW
100ms
V
D
2.70
2.40
V
RST
13.3.
Power-fail Reset
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply monitor
will drive the /RST pin low and return the CIP-51 to the reset state (see Figure 13.2). When VDD returns to a level
above VRST, the CIP-51 will leave the reset state in the same manner as that for the power-on reset. Note that even
though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD
dropped below the level required for data retention. If the PORSF flag is set, the data may no longer be valid.
Rev. 1.7
94
相關(guān)PDF資料
PDF描述
LM4040C25QDBZTG4 IC VREF SHUNT PREC 2.5V SOT-23-3
LB2016T330K INDUCTOR WOUND 33UH 85MA 0806
GEM12DTMN-S189 CONN EDGECARD 24POS R/A .156 SLD
LM4040C25IDBZTG4 IC VREF SHUNT PREC 2.5V SOT-23-3
GEM12DTMH-S189 CONN EDGECARD 24POS R/A .156 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
C8051F005DK-A 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類別:編程器,開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK(80-QFP ZIF 插口) 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊 其它名稱:520-1035
C8051F005DK-B 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類別:編程器,開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK(80-QFP ZIF 插口) 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊 其它名稱:520-1035
C8051F005DK-E 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類別:編程器,開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK(80-QFP ZIF 插口) 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊 其它名稱:520-1035
C8051F005DK-H 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類別:編程器,開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK(80-QFP ZIF 插口) 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊 其它名稱:520-1035
C8051F005DK-J 功能描述:DEV KIT FOR C8051F005/F006/F007 RoHS:否 類別:編程器,開發(fā)系統(tǒng) >> 過時/停產(chǎn)零件編號 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:MCU 適用于相關(guān)產(chǎn)品:Freescale MC68HC908LJ/LK(80-QFP ZIF 插口) 所含物品:面板、纜線、軟件、數(shù)據(jù)表和用戶手冊 其它名稱:520-1035