參數(shù)資料
型號: C3ENPA1-DS
英文描述: 5.0 or 3.3V, 256Kbit (32Kbit x 8) ZEROPOWER® SRAM
中文描述: ? - 3E的網(wǎng)絡處理器的數(shù)據(jù)資料硅修訂格A1
文件頁數(shù): 90/114頁
文件大?。?/td> 1893K
代理商: C3ENPA1-DS
90
CHAPTER 3: ELECTRICAL SPECIFICATIONS
C3ENPA1-DS/D REV 03
MOTOROLA GENERAL BUSINESS INFORMATION
Low Speed Serial Interface Timing Specifications
The low speed serial interface timing is shown in
Figure 21
and described in
Table 46
.
Figure 21
Low Speed Serial Interface Timing Diagram
Cycle 2
Cycle 3
T
slc
T
slss
T
slhd
T
slsd
T
slhs
SICL
SIDA
T
slst
T
slb
Table 46
Low Speed Serial Interface Timing Description
SYMBOL
PARAMETER
MIN
MAX
UNIT
Tslc
SICL Cycle Time
2500
ns
Tslss
Set-up Time for Repeated START Condition
600
ns
Tslhs
Hold Time START Condition
600
ns
Tslsd
Data Set-up Time
250
ns
Tslhd
Data Hold Time
0.0
ns
Tslst
Set-up Time for STOP Condition
600
ns
Tslb
Bus Free Time Between a STOP and START Condition
1250
ns
Cmax
Capacitive load for each line of the bus
400
pF
F
n
.
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