參數(shù)資料
型號： C3ENPA1-DS
英文描述： 5.0 or 3.3V, 256Kbit (32Kbit x 8) ZEROPOWER® SRAM
中文描述： ? - 3E的網(wǎng)絡(luò)處理器的數(shù)據(jù)資料硅修訂格A1
文件頁數(shù)： 37/114頁
文件大?。?/td> 1893K
代理商： C3ENPA1-DS
Pin Descriptions Grouped by Function
37
MOTOROLA GENERAL BUSINESS INFORMATION
C3ENPA1-DS/D REV 03
Table 11
Gigabit Ethernet (GMII/MII) Signals One Cluster Example
SIGNAL NAME*
PIN #
TOTAL
TYPE
I/O
LABEL
SIGNAL DESCRIPTION
CP
n
_0
Table 7
1
LVTTL
O
PD
T_CLK
GMII Transmit Clock (125MHz). This clock is used to synchronize the
transmit data.
CP
n
_1
Table 7
1
LVTTL
I
PU
TCLKI
MII transmit clock. Transmit data aligned to this clock input from
phy in MII mode. 25 Mhz in 100BaseT, 2.5 in Mhz in 10BaseT
CP
n
_2
Table 7
1
LVTTL
O
PD
O
PU
O
PD
O
PU
O
PU
TXD(0)
Transmit Data (byte-wide data, least significant bit)
CP
n
_3
Table 7
1
LVTTL
TXD(1)
Transmit Data
CP
n
_4
Table 7
1
LVTTL
TXD(2)
Transmit Data
CP
n
_5
Table 7
1
LVTTL
TXD(3)
Transmit Data
CP
n
_6
Table 7
1
LVTTL
TX_EN
Transmit Enable. When asserted, the data on TXD is encoded and
transmitted on the twisted pair cable.
CP
n+1
_0
Table 7
1
nc
nc
PD
I
PU
nc
nc
CP
n+1
_1
Table 7
1
LVTTL
COL
Collision. Asserted when both RX_DV and TX_EN are valid during
half duplex operation.
CP
n+1
_2
Table 7
1
LVTTL
O
PD
O
PU
O
PD
O
PU
O
PU
TXD(4)
Transmit Data
CP
n+1
_3
Table 7
1
LVTTL
TXD(5)
Transmit Data
CP
n+1
_4
Table 7
1
LVTTL
TXD(6)
Transmit Data
CP
n+1
_5
Table 7
1
LVTTL
TXD(7)
Transmit Data (byte-wide receive data, most significant bit)
CP
n+1
_6
Table 7
1
LVTTL
TX_ER
Transmit Error. Asserting TX_ER when TX_EN is a 1 causes
transmission of the designated
“
bad code
”
in lieu of the normal
encoded data on the twisted pair data.
CP
n+2
_0
Table 7
1
nc
nc
PD
I
PU
I
PD
I
PU
I
PD
I
PU
I
PU
nc
nc
CP
n+2
_1
Table 7
1
LVTTL
RCLK
Receive Clock (125MHz)
CP
n+2
_2
Table 7
1
LVTTL
RXD(0)
Receive Data (byte-wide receive data, least significant bit)
CP
n+2
_3
Table 7
1
LVTTL
RXD(1)
Receive Data
CP
n+2
_4
Table 7
1
LVTTL
RXD(2)
Receive Data
CP
n+2
_5
Table 7
1
LVTTL
RXD(3)
Receive Data
CP
n+2
_6
Table 7
1
LVTTL
RX_DV
Receive Data Valid. Indicates that there is a receive frame in progress
and that the data present on the RXD signals is valid.
CP
n+3
_0
Table 7
1
nc
nc
PD
I
PU
nc
nc
CP
n+3
_1
Table 7
1
LVTTL
CRS
Carrier Sense. Indicates traffic is on the link. CRS is asserted when a
non-idle condition is detected on the receive data stream. CRS is
deasserted when an end of frame or idle condition is detected.
F
n
.
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