參數(shù)資料
型號(hào): C3ENPA1-DS
英文描述: 5.0 or 3.3V, 256Kbit (32Kbit x 8) ZEROPOWER® SRAM
中文描述: ? - 3E的網(wǎng)絡(luò)處理器的數(shù)據(jù)資料硅修訂格A1
文件頁數(shù): 54/114頁
文件大?。?/td> 1893K
代理商: C3ENPA1-DS
54
CHAPTER 2: SIGNAL DESCRIPTIONS
C3ENPA1-DS/D REV 03
MOTOROLA GENERAL BUSINESS INFORMATION
QMU SRAM (Internal
Mode) Interface Signals
The QMU signals are described in
Table 24
.
Table 24
QMU SRAM (Internal Mode) Interface Signals
SIGNAL NAME
PIN #
TOTAL
TYPE
I/O
SIGNAL DESCRIPTION
QA0 - QA16
D10, C10, A10, F11, E11, D11, C11, B11, A11, F12,
E12, D12, C12, A12, F13, E13, D13
17
LVTTL
O
Address [16:0]
QD0 - QD31
F1, E1, D1, C1, B1, F2, E2, C2, A2, E3, D3, C3, B3, A3,
D4, B4, A4, E5, D5, C5, B5, A5, E6, C6, A6, E7, D7,
C7, B7, A7, E8, D8
32
LVTTL
I
PD
/O Data
QDQPAR
C8
1
LVTTL
I
PD
I
PD
I
PD
O
nc
QARDY
F10
1
LVTTL
nc
QNQRDY
A9
1
LVTTL
nc
QWEX
E10
1
LVTTL
Write Enable
QBCLKO
B8
1
LVTTL
O
nc
QBCLKI
A8
1
LVTTL
I
PD
O
nc
QACLKO
F9
1
LVTTL
nc
QACLKI
E9
1
LVTTL
I
PD
I
PD
/O Data Parity Low
I
PD
/O Data Parity High
Input Clock
QDPL
C9
1
LVTTL
QDPH
B9
1
LVTTL
TOTAL PINS
59
F
n
.
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