![](http://datasheet.mmic.net.cn/180000/BT2166AHF_datasheet_11281796/BT2166AHF_65.png)
Bt2166
Graphics/Video Controller
Brooktree
36
VGA IMPLEMENTATION
Support for VESA BIOS Extension Modes
L2166_A
Mode Setting Procedure
The steps required to initialize a VBE mode depend on two factors:
Does the mode use a VGA-compatible memory model? If not, the VGA
hardware must be disabled through the ENABLE_VGA_CRT bit.
Can the mode use VGA-generated DREF register values? If not, the
ENABLE_VGA_CRT_GEN should be set to ‘0’ to disable timing data
generation. BIOS must program the DREF registers.
In general, the procedure is as follows:
1
Initialize DREF register set if not already initialized. Initialize the regis-
ter elds which congure the VGA module.
2
If the mode does not use a VGA-compatible memory model (VBE mod-
els 0 through 4), then disable VGA CRT Controller functionality by
clearing the ENABLE_VGA_CRT bit (bit 2 of GRP_CFG4). In this case,
enable the real-mode or protected-mode aperture.
3
If the resolution exceeds standard VGA modes (such as 720 X 400 or 640
X 480), disable generation of the DREF register values. Program the
DREF registers directly with the mode’s timing parameters.
4
Modify the Pixel Clock PLL register. If the 25 MHz or 28 MHz pixel
clock will be selected through the VGA Miscellaneous Output register,
then the pixel clock eld does not need to be modied. The VGA will
generate the Pixel Clock PLL value automatically. Otherwise, write a
10b to bits 3 and 2 of the Miscellaneous Output register.
Logical Window Control
The VBE functions include logical window setup and control (such as setting the
logical line width and adjusting the display start address). These functions can be
used for horizontal panning, vertical scrolling, and display buffer switching for an-
imation.
The Bt2166 chip provides the capability to support these functions in hardware.
The easiest way to accomplish all of these functions is to change the graphics start
address pointer in the DREF by writing to the active graphics start register, the de-
fault register being Graphics Start Address A. Alternatively, any one of the DREF’s
three start address registers (A,B, and C) can be selected manually or automatical-
ly between frames. However, manual selection provides little advantage over sim-
ply writing a new value to the default active register.
Horizontal panning is a little more difcult if you want more resolution than a
quadword’s worth of pixels. It is possible though. The DREF architecture differ-
entiates between an “active region” in the screen and the “graphics window”. They
are usually the same, but they don’t have to be. By having the graphics window be-
ing larger than the active region, you can simulate panning by moving the graphics
window underneath the active region, one pixel width at a time.
DAC Palette Format
The VBE includes a function to set/get the number of bits per palette primary color.
For palette access via the VGA 3C9h port, the Bt2166 controller supports both 6-
bit and 8-bit formats, which are the most common formats. The selection is made
through bit 0 of the GRP_VGACFG register. A ‘1’ indicates an 8-bit mode, while
a ‘0’ indicates a 6-bit mode (refer to “VGA Conguration Register” on page 45).
This bit only affects accesses via the VGA 3C9h port. When congured for 6-
bit modes, palette operations via 3C9h are translated between 6-bit and 8-bit for-
mats. On the other hand, any palette values programmed directly through the
DREF palette registers are always in 8-bit format. However, BIOS can still per-
form the translation if the palette is accessed through the Load/Unload Palette Data
function call.