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L2166_A
I2C Register Denitions
I2C Master Module Software Interface
Bt2166
Graphics/Video Controller
Table 67. I2C Master Write Control Register GRP_I2C_MCTRLW[7:0] Bit Descriptions
(1 of 2)
Bit
Function
Detail
7
Unused
This bit is currently unused in the I2C master module, however the system software must
always write “0” here to allow for possible future expansions.Must write 0 here.
6
400K
400 kHz mode. When set to “1,” the 400 K control bit causes the I2C master module to transmit
at the full speed 400 kHz clock rate. When set to “0,” it uses a more conservative 100 kHz clock
rate (actually the rate is only 8 0kHz but the timings are set up to satisfy the I2C 100 kHz mode
spec).
0 = 100 kHz mode
1 = 400 kHz mode
5(1)
TSTO
Transmit a stop. When set to “1,” the TSTO control bit causes the I2C master module to trans-
mit a stop token onto the I2C bus. If this I2C master module is not bus master, then this control
bit will be ignored. Note that unlike TSTA and TRAN, it is not possible to combine TSTO with
TRAN or RECV. A separate command access by the system software is required to transmit a
stop to the I2C bus. Thus if TRAN, RECV, or TSTA are set to “1” then TSTO must be “0.”
0 = not transmit a stop
1 = transmit a stop
4(1)
TSTA
Transmit a start. When set to “1” the TSTA control bit causes the I2C master module to transmit
a start token onto the I2C bus. If the bus is busy, it will wait for the bus to become free before
transmitting the start token. If this I2C master module is already bus master, it will transmit the
start token immediately. If the TRAN control bit is also set to “1,” the I2C master will transmit the
contents of the
GRP_I2C_MDATA register immediately after the start token. The combination
where both the TSTA and TSTO bits are written as “1” is illegal and the operation of the I2C
master module is not dened.
0 = not transmit a start
1 = transmit a start
3
INTE
Interrupt enable. When set to “1,” the INTE control bit causes the interrupt output from the I2C
master module to go to “1” whenever the contents of the DONE eld goes to “1” (i.e. at the end
of a transmit or receive or arbitration loss). If this bit is set to “0,” the system software must ser-
vice the I2C bus by means of software polling. This action will not result in the loss of any data
but may cause the I2C bus stand idle until the system software next polls this module and sets
up the next request. The actual interrupt is generated by ANDing this bit with the DONE bit of
the GRP_I2C_MCTRLR Read register.
0 = disable interrupts (software polling)
1 = interrupt enable
2
TACK
Acknowledge to transmit. The TACK bit contains the value that the I2C master module will
transmit whenever it needs to transmit an acknowledge bit. (i.e., whenever it needs to acknowl-
edge a I2C reception.). Value of last I2C acknowledge bit received
1(1)
RECV
Receive data. When set to “1,” the RECV bit will start the process of receiving the contents of
the GRP_I2C_MDATA register from the I2C bus. Note that the I2C master module must already
be bus master (MAST = 1 in the GRP_I2C_MCTRLR register). Note also that since the I2C
spec does not allow any circumstance where the I2C master follows a start with anything other
than a transmit, this module does not support combining the action of the TSTA bit with the
RECV bit as it does with TSTA and TRAN to enable both a start and transmit. The combination
where both the RECV and TSTA bits are written as “1” is illegal and the operation of the I2C
master module is not dened if this happens.
0 = no receive data
1 = receive data