
99
L2166_A
I2C Register Denitions
I2C Slave Module Software Interface
Bt2166
Graphics/Video Controller
Minimum Stop Transaction
The I2C spec guarantees a minimum of 1.3
s between a stop transaction and a fol-
lowing start transaction on the I2C bus, so if the software interrupt service routing
can guarantee to service the interrupt in less than 1.3
s there won’t be a problem.
If there is any doubt that the software interrupt service routine can service a break
on stop interrupt quickly enough then the break on stop condition must be com-
bined with another break request (break on start, break on receive or break on ac-
knowledge) to allow the I2C slave module to continue with the next reception
without loss of data. When this is done the software interrupt service routine must
check for the possibility that both break conditions (break on stop and the other
break condition) have occurred when servicing the interrupt and take appropriate
action if the second break condition has also occurred to avoid missing the second
interrupt.
Note also that any of the above break conditions except for BSTO (Break on
stop) will cause the I2C slave module to hold the I2C bus idle until the
GRP_I2C_SCTRLW register is written again with a new request. It is the respon-
sibility of the system software to ensure that the GRP_I2C_SCTRLW register is
written to un-idle the I2C bus within a reasonable period of time. The system soft-
ware is also responsible for ensuring that the I2C slave module is given a new re-
quest sufciently fast after a break on stop condition. This is necessary because the
break on stop does not idle the I2C bus, which could therefore begin another trans-
action while the I2C slave module is still waiting for system software service, caus-
ing the loss of data. Fortunately it is never necessary to detect a break on stop
condition in the normal operation of the I2C; the system software could easily ig-
nore the stop token and instead break on start to detect the start of the next I2C bus
transaction. Also, the I2C spec requires that the I2C bus remain idle for 1.3
s after
the transmission of a stop token, guaranteeing the system software at least 1.3
s to
respond to the break on stop request.
Passive I2C Bus Snooper
It is possible to use the I2C slave module as a completely passive I2C bus snooper.
Set the GRP_I2C_SCTRLW register to break at the various points of interest in the
I2C transactions and set the TACK bit to “1.” Data is received as in normal I2C
slave module operations, but you can also see what value ACK bit was transmitted
by looking at the value of the LOST bit in the GRP_I2C_SCTRLR register. If the
ACK bit on the I2C bus was “0,” the LOST bit will be set to “1” (since the I2C slave
module was trying to send an ACK of 1 and saw an ACK of “0,” it sets the LOST
bit). Similarly an ACK bit of “1” on the I2C bus will cause the LOST bit in the
GRP_I2C_SCTRLR register to remain at zero. To ensure that the I2C slave module
is completely passive, all the “break on something” conditions must be serviced
immediately. Polling or interrupting is not sufcient because the I2C slave module
might halt the I2C bus if it is left waiting for software service for too long. Table 74
gives an example of possible settings of the GRP_I2C_SCTRLW bits.