![](http://datasheet.mmic.net.cn/180000/BT2166AHF_datasheet_11281796/BT2166AHF_57.png)
Bt2166
Graphics/Video Controller
Brooktree
28
VGA IMPLEMENTATION
VGA Operation
L2166_A
VGA Operation
This specication does not intend to dene the VGA architecture and functional-
ity; application programmers should consult a book on the subject. However, the
“I/O Mapped Register Denitions” chapter provides a list of VGA registers, in-
cluding I/O addresses, read/write capability, and a list of the elds within that reg-
ister. In the meantime, below are some notes about the Bt2166 implementation.
Simultaneous Operation
with Other Bt2166
Modules
The BtVista hardware does not preclude the simultaneous operation of the VGA
and GUI or VGA and video modules. However, such operations are usually not
feasible because VGA applications typically do not include a driver-based inter-
face to GUI or video functionality. The Bt2166 design assumes (but does not re-
quire) that GUI and video applications will run with VGA hardware disabled, and
provides drivers accordingly. A GUI application could run using a standard VGA
driver, but typically the GUI block would be disabled and only the VGA module
enabled. Whether motion video applications work with a VGA graphics driver is a
design choice in the coding of the Bt2166 low-level video driver.
A full-screen DOS window within Windows would also take advantage of the
VGA hardware. However, when switching to a full-screen DOS window, the GUI
hardware is typically disabled, so that again GUI and VGA hardware are not actu-
ally enabled concurrently.
VGA and DREF
The VGA denition originally assumed that the VGA hardware directly drove the
monitor timing signals and directly sequenced pixel data to a palettized RAM-
DAC. This was done through a VGA submodule called the CRT Controller. In fact,
the Bt2166 VGA module does not directly drive monitor sync signals nor does it
directly output data to the DAC. Instead, the Bt2166 implements a Display Refresh
(DREF) module (refer to “Display Refresh Controller” on page 179), requiring the
Bt2166 VGA module to implement some unique mechanisms to emulate the VGA
CRT Controller functionality. The VGA module must automatically program the
DREF monitor timing registers based on the VGA CRT register contents. It must
also read in the VGA frame buffer and convert it into 8-bit pixel data which it stores
in a DRAM buffer area for the DREF to later read.
The source VGA frame buffer is always stored in a 256 KB region starting at ad-
dress zero of the DRAM media buffer, while the resultant 8-bit-per-pixel screen
image is always output to the second 256 KB region of the DRAM media buffer
starting at adresss 40000h.
The Bt2166 has dual paths to the DREF registers. One path goes directly from
the PCI bus, and the other path goes indirectly through the VGA module. The VGA
DREF writes are triggered by writes to a subset of VGA registers. Software can
modify the DREF registers directly, but they might be overwritten the next time
software writes to a VGA register.