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Bt2166
Graphics/Video Controller
Brooktree
32
VGA IMPLEMENTATION
VGA Extension Register Control and Status
L2166_A
VGA Extension Register Control and Status
The Bt2166 provides some additional register elds which are not VGA standard
registers but enable software to congure or monitor the VGA. These implemen-
tation-specic registers are located in the VGA Graphics Controller Extension
space. In other words, they are accessed through the 3CEh, 3CFh indexing mech-
anism at register indices that lie above those dened for the VGA graphics con-
troller. The chip provides a mechanism to lock or unlock access to these extended
registers. However, not all registers in that space are related to VGA; hence not all
are listed below.
For instructions on unlocking VGA extension registers, refer to “Unlock Regis-
ter” on page 60. The VGA elds are summarized below.
Enable VGA CRT
Controller Mechanism
The ENABLE_VGA_CRTC eld in the GRP_CFG4 register (bit 2, index 44h) en-
ables the VGA module to write pixel data to the frame buffer RAM and acts as
master enable for modifying DREF registers. If disabled, no pixel data will be
written and DREF registers will not be modied by the VGA hardware. If enabled,
the ENABLE_VGA_CRTC_GEN bit (bit 7, index 45h) must also be enabled in or-
der to allow modication of DREF registers. If ENABLE_VGA_CRTC_GEN is
off, the VGA will still be allowed to write graphics data to the RAM, but will not
disable access to VGA I/O registers or the VGA memory-mapped frame buffer.
Enable VGA CRT
Controller DREF
Programming
The ENABLE_VGA_CRTC_GEN eld in the GRP_CFG5 register (bit 7, index
45h) enables the VGA module to program the DREF timing registers (see Table 25
on page 52). This bit is only effective if the ENABLE_VGA_CRTC bit (bit 2, in-
dex
44h)
is
set
also.
Setting
ENABLE_VGA_CRTC
but
resetting
ENABLE_VGA_CRTC_GEN to zero does have a purpose. It allows software to
directly program the monitor timing and resolution while still using the VGA to
generate pixel data. This has an application in VGA-compatible VESA BIOS
modes. Note that this bit does not disable the generation of pixel data, translation
of VGA palette access to DREF palette access, translation of VGA border color
writes to VGA border color writes, nor the VGA’s ability to override the Pixel
Clock PLL register.
25 MHz PLL Select
Registers GRP_25PLL1 (index 1Bh) and GRP_25PLL0 (index 1Ah) specify the
M, N, and L values that control the Pixel Clock PLL when the VGA Miscellaneous
Output register is set for a 25 MHz pixel clock. Refer to “PLL25 Select Registers”
on page 45.
28 MHz PLL Select
Registers GRP_28PLL1 (index 1Eh) and GRP_28PLL0 (index 1Dh) specify the
M, N, and L values that control the Pixel Clock PLL when the VGA Miscellaneous
Output register is set for a 28 MHz pixel clock. Refer to “PLL28 Select Registers”
on page 46.