Brooktree
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VGA IMPLEMENTATION
Support for VESA BIOS Extension Modes
L2166_A
Bt2166
Graphics/Video Controller
Support for VESA BIOS Extension Modes
The VESA BIOS Extension (VBE) specication denes standard BIOS function
calls which provide software access to resolutions, color depths, and frame buffer
organizations beyond the VGA hardware standard. The Bt2166 supports these
VESA BIOS extensions. These extensions have often been referred to as Super
VGA (SVGA) modes.
VBE Modes
The Bt2166 hardware supports all VBE functions and common modes. The VESA
modes that use VGA-compatible memory models allow the application to take ad-
vantage of VGA hardware. Those that use 256-color non-chain-4 and direct color
memory models are supported, but without VGA hardware. In these modes the
Bt2166 behaves as a dumb frame buffer controller supporting 8-bit color depths.
VGA IO operations will affect neither the frame buffer accesses nor the display
format. Status and control functions should be done through calls to the VBE func-
tions, with the following exceptions: the DAC palette (3C6-3C9h), Attribute Over-
scan (3c0, index 11), and Input Status 1 (3DAh) still function upon disabling the
VGA.
Frame Buffer Models
The VBE specication denes two ways to implement a frame buffer aperture:
VGA window or linear/at model. The set mode function includes an extra bit
which species which model to use. The Bt2166 supports both.
For the VGA windowing frame buffer model, the Bt2166 provides dual real
mode apertures via VGA address space. Each port may be congured for a 32 K or
64 K window size. The 32 K and 64 K mode aperture addresses are dened in
"GRP_GUI_BASE Address Register," Table 16 on page 47. Each port includes
read/write capability and a paging mechanism which allows an application to
“window” into the frame buffer.
For the linear/at buffer model, the Bt2166 chip provides a protected mode ap-
erture which can be located anywhere within the CPU’s 32-bit address space. For
more information, refer to “Real Mode Aperture” on page 25.
DREF register
Programming and High-
Resolution Modes
The VGA DREF register programming mechanism supports applications that
change modes by writing directly to VGA CRT Controller Registers, rather than
making a BIOS call. However, the VGA registers do not provide all of the exi-
bility that programming the DREF registers directly provides. For example, VGA
always programs the DREF for 8 or 9 pixel timing. This limits the timing resolu-
tion that can be achieved. Also, there is no standard mechanism for switching to
high-resolution modes independently of making a BIOS call. Therefore, it is wiser
for BIOS or application drivers to program the DREF registers directly rather than
rely on the VGA hardware to do it. This also means that the VGA DREF program-
ming mechanism must be disabled by clearing the ENABLE_VGA_CRT_GEN
bit (bit 7) in the GRP_CFG5 register (see Table 25 on page 52).