參數(shù)資料
型號(hào): BQ2083
英文描述: Silicon Bridge Rectifiers
中文描述: 銀紫荊星章符合電量監(jiān)測(cè)計(jì)芯片的使用與BQ29311
文件頁(yè)數(shù): 6/54頁(yè)
文件大小: 461K
代理商: BQ2083
SLUS573 JULY 2003
www.ti.com
6
SMBUS TIMING SPECIFICATIONS
VDD = 3.0 V to 3.6 V, TA = 20
°
C to 85
°
C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fSMB
fMAS
tBUF
thd(STA)
tsu(STA)
tsu(STO)
SMBus operating frequency
Slave mode, SMBC 50% duty cycle
10
100
kHz
SMBus master clock frequency
Master mode, no clock low slave extend
51.2
kHz
μ
s
μ
s
μ
s
μ
s
Bus free time between start and stop
4.7
Hold time after (repeated) start
4.0
Repeated start setup time
4.7
Stop setup time
4.0
thd(DAT)
Data hold time
Receive mode
0
ns
Transmit mode
300
tsu(DAT)
tTIMEOUT
tlow
thigh
tlow(SEXT)
tlow(MEXT)
tf
tr
(1)The bq2083V1P2 times out when any clock low exceeds tTIMEOUT
(2)thigh Max. is minimum bus idle time. SMBC = 1 for t > 50
μ
s causes reset of any transaction involving bq2083V1P2 that is in progress.
(3)tlow(SEXT) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4)tlow(MEXT) is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop.
(5)Rise time tr = (VILMAX 0.15 V) to (VIHMIN + 0.15 V).
(6)Fall time tf = 0.9 VDD to (VILMAX 0.15 V).
Data setup time
250
ns
Error signal/detect
See Note 1
25
35
ms
μ
s
μ
s
ms
Clock low period
4.7
Clock high period
See Note 2
4.0
50
Cumulative clock low slave extend time
See Note 3
25
Cumulative clock low master extend time
See Note 4
10
ms
Clock/data fall time
See Note 5
300
ns
Clock/data rise time
See Note 6
1000
ns
DATA FLASH MEMORY SWITCHING CHARACTERISTICS
VDD = 3.0 V to 3.6 V, TA = 20
°
C to 85
°
C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
See Note 1
MIN
10
TYP
MAX
UNIT
Years
t(RETENSION)
Data retention
Flash programming write-cycles
See Note 1
105
Cycles
t(WORDPROG)
I(DDPROG)
(1)Specified by design. Not production tested.
Word programming time
See Note 1
2
ms
Flash-write supply current
See Note 1
14
16
mA
Register Backup
PARAMETER
TEST CONDITIONS
VRB > 3.0 V, VDD < VIT
MIN
TYP
10
MAX
100
UNIT
nA
I(RBI)
V(RBI)
(1)Specified by design. Not production tested.
RBI data-retention input current (see Note 1)
RBI data-retention voltage
1.3
V
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