參數(shù)資料
型號(hào)： BQ2083
英文描述： Silicon Bridge Rectifiers
中文描述： 銀紫荊星章符合電量監(jiān)測(cè)計(jì)芯片的使用與BQ29311
文件頁(yè)數(shù)： 20/54頁(yè)
文件大?。?/td> 461K
代理商： BQ2083
SLUS573 JULY 2003
www.ti.com
20
Device Reset
The following procedure resets the bq2083V1P2:
1.
2.
Write 0x653 to Address 0. (This puts the device in calibration mode.)
Write 0x000 to Address 5E. (This puts the device back into normal mode.)
NOTE: No other write actions should be attempted between step 1 and step 2.
COMMUNICATION
The bq2083V1P2 includes an SMBus communication port. The SMBus interface is a 2-wire bidirectional protocol
using the SMBC (clock) and SMBD (data) pins. The communication lines are isolated from VCC and may be pulled-up
higher than V
CC
. Also, the bq2083V1P2 does not pull these lines low if V
CC
to the part is zero.
The communication ports allow a host controller, an SMBus compatible device, or other processor to access the
memory registers of the bq2083V1P2. In this way a system can efficiently monitor and manage the battery.
SMBus
The SMBus interface is a command-based protocol. A processor acting as the bus master initiates communication
to the bq2083V1P2 by generating a start condition. A start condition consists of a high-to-low transition of the SMBD
line while the SMBC is high. The processor then sends the bq2083V1P2 device address of 0001011 (bits 7-1) plus
a R/W bit (bit 0) followed by an SMBus command code. The R/W bit (LSB) and the command code instruct the
bq2083V1P2 to either store the forthcoming data to a register specified by the SMBus command code or output
the data from the specified register. The processor completes the access with a stop condition. A stop condition
consists of a low-to-high transition of the SMBD line while the SMBC is high. With SMBus, the most-significant bit
(MSB) of a data byte is transmitted first.
In some instances, the bq2083V1P2 acts as the bus master. This occurs when the bq2083V1P2 broadcasts
charging requirements and alarm conditions to device addresses 0x12 (SBS Smart Charger) and 0x10 (SBS Host
Controller).
SMBus Protocol
The bq2083V1P2 supports the following SMBus protocols:
Read word
Write word
Block read
A processor acting as the bus master uses the three protocols to communicate with the bq2083V1P2. The
bq2083V1P2 acting as the bus master uses the write word protocol.
The SMBD and SMBC pins are open drain and require external pullup resistors. A 1-M
pulldown resistor in the
battery pack on SMBC and SMBD is required to assure the detection of the SMBus offstate, the performance of
automatic offset calibration, and the initiation of the low-power sleep mode when the battery pack is removed.
SMBus Packet Error Checking
The bq2083V1P2 supports packet error checking as a mechanism to confirm proper communication between it and
another SMBus device. Packet error checking requires that both the transmitter and receiver calculate a packet error
code (PEC) for each communication message. The device that supplies the last byte in the communication message
appends the PEC to the message. The receiver compares the transmitted PEC to its PEC result to determine if there
is a communication error.
PEC Protocol
The bq2083V1P2 can receive or transmit data with or without PEC. Figure 6 shows the communication protocol
for the read word, write word, and read block messages without PEC. Figure 7 includes PEC.
In the read word protocol, the bq2083V1P2 receives the PEC after the last byte of data from the host. If the host
does not support PEC, the last byte of data is followed by a stop condition. After receipt of the PEC, the bq2083V1P2
compares the value to its calculation. If the PEC is correct, the bq2083V1P2 responds with an ACKNOWLEDGE.
If it is not correct, the bq2083V1P2 responds with a NOT ACKNOWLEDGE and sets an error code.
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