2002 Teccor Electronics
Thyristor Product Catalog
AN1002 - 1
http://www.teccor.com
+1 972-580-7777
AN1002
Gating, Latching, and Holding of SCRs and Triacs
Introduction
Gating, latching, and holding currents of thyristors are some of
the most important parameters. These parameters and their
interrelationship determine whether the SCRs and triacs will
function properly in various circuit applications.
This application note describes how the SCR and triac parame-
ters are related. This knowledge helps users select best operat-
ing modes for various circuit applications.
Gating of SCRs and Triacs
Three general methods are available to switch thyristors to
on-state condition:
Applying proper gate signal
Exceeding thyristor static dv/dt characteristics
Exceeding voltage breakover point
This application note examines only the application of proper
gate signal. Gate signal must exceed the I
and V
require-
ments of the thyristor being used. I
GT
(gate trigger current) is the
minimum gate current required to switch a thyristor from the off
state to the on state. V
(gate trigger voltage) is the voltage
required to produce the gate trigger current.
SCRs (unilateral devices) require a positive gate signal with
respect to the cathode polarity. Figure AN1002.1 shows the cur-
rent flow in a cross-sectional view of the SCR chip.
Figure AN1002.1
SCR Current Flow
In order for the SCR to latch on, the anode-to-cathode current (I
T
)
must exceed the latching current (I
) requirement. Once latched
on, the SCR remains on until it is turned off when anode-to-cath-
ode current drops below holding current (I
H
) requirement.
Triacs (bilateral devices) can be gated on with a gate signal of
either polarity with respect to the MT1 terminal; however, differ-
ent polarities have different requirements of I
and V
.
Figure AN1002.2 illustrates current flow through the triac chip in
various gating modes.
Figure AN1002.2
Triac Current Flow (Four Operating Modes)
P
N
N
P
Anode
Cathode
Gate
(+)
(-)
(+)I
T
I
GT
N
N
N
N
N
N
P
P
P
P
Gate(+)
I
GT
MT1(-)
N
N
IT
MT2(+)
QUADRANT I
Gate(-)
I
GT
MT1(-)
MT2(+)
QUADRANT II
N
N
N
N
N
N
N
N
P
P
P
P
Gate(+)
I
GT
MT1(+)
I
GT
QUADRANT III
Gate(-)
MT1(+)
MT2(-)
QUADRANT IV
I
T
I
T
MT2(-)
AN1002