
ASIX ELECTRONICS CORPORATION
81
AX88796BLF / AX88796BLI
Reversion History
Revision
V1.0
V1.1
Date
2006/03/01
2006/03/31
Comment
Initial Release.
1. Correct some typo errors.
2. Change page3 offset 0Dh register name from P30D to MISC.
3. Change the name of bit 5 of MCR register from TQCE to BBTC.
4. Define a short name “TXCQF” for bit 7 of CTEPR register.
5. Add the default values of PHY registers into Section 5.2.
1. Correct the pin descriptions of pin 60 and 63 in Figure 2 and Section
2-5.
2. Correct the Wakeup Frame registers configuration information in
Section 4.3.1.
3. Update the reference schematics in Section 7.3.2, Appendix A1.
4. Remove Demonstration Circuit A, B, C reference schematics.
1. Modify the resistance value of pin 64 (RSET_BG) from 11.8
±
1% K
ohm to 12.1
±
1% K ohm.
1. Add Thermal Resistance values (
Θ
Jc,
Θ
JA
) of Junction in Section
7.3.2.
2. Correct the SD[7:0] values of Read cycle in Appendix A3 “186-like
(16-bit)”.
3. Correct the SD[7:0] and SD[15:8] values of offset 1Fh register Read
cycle in Appendix A1~A4.
1. Add US patent approved (NO 6799231) and VLAN in the Features
page.
2. Change the product name in the Features page.
3. Correct the TPI+/TPI- pin name of AX88796B Pin Out Diagram in
Section 1.3.
4. Modify some pin descriptions in Section 2.2 and 2.5.
5. Modify the Wake-up Configuration descriptions in Section 4.3.1 and
5.1.54.
6. Change the Storage Temperature to –65 to 150
°
C in Section 7.1.
7. Add Appendix A5 to indicate the reference connection for big-endian
processor.
8. Add Appendix B to indicate how to disable the internal regulator.
1. Modify the description of SA5/FIFO_SEL pin in Section 2.1 and
Appendix A4.
2. Swapped the pin name of XTALIN and XTALOUT in Section 2.5
and Figure 2.
1. Correct a typo in Revision History table.
2. Add some information into Section 7.2.
V1.2
2006/09/08
V1.3
2006/09/20
V1.4
2006/10/05
V1.5
2007/3/19
V1.6
2007/4/27
V1.7
2007/8/18