參數(shù)資料
型號： AX88796BLI
廠商： ASIX Electronics Corporation
英文描述： Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
中文描述： 低引腳數(shù)的非PCI 16位產(chǎn)品10/100M自適應(yīng)快速以太網(wǎng)控制器
文件頁數(shù)： 16/82頁
文件大?。?/td> 519K
代理商： AX88796BLI
ASIX ELECTRONICS CORPORATION
16
AX88796BLF / AX88796BLI
Initialization Of The Buffer Ring
Two static registers and two working registers control the operation of the Buffer Ring. These are the Page Start
Register, Page Stop Register (both described previously), the Current Page Register and the Boundary Pointer
Register. The Current Page Register points to the first buffer used to store a packet and is used to restore the DMA
for writing status to the Buffer Ring or for restoring the DMA address in the event of a Runt packet, a CRC, or
Frame Alignment error. The Boundary Register points to the first packet in the Ring not yet read by the host. If the
local DMA address ever reaches the Boundary, reception is aborted. The Boundary Pointer is also used to initialize
the Remote DMA for removing a packet and is advanced when a packet is removed. A simple analogy to remember
the function of these registers is that the Current Page Register acts as a Write Pointer and the Boundary Pointer acts
as a Read Pointer.
Buffer #1
Buffer #2
Buffer #3
…
…
…
…
Buffer #n
Physical Memory Map
Logic Receive Buffer Ring
Fig - 5 Receive Buffer Ring At Initialization
Beginning Of Reception
When the first packet begins arriving the AX88796B and begins storing the packet at the location pointed to by the
Current Page Register. An offset of 4 bytes is reserved in this first buffer to allow room for storing receives status
corresponding to this packet.
Linking Receive Buffer Pages
If the length of the packet exhausts the first 256 bytes buffer, the DMA performs a forward link to the next buffer to
store the remainder of the packet. For a maximal length packet the buffer logic will link six buffers to store the entire
packet. Buffers cannot be skipped when linking; a packet will always be stored in contiguous buffers. Before the
next buffer can be linked, the Buffer Management Logic performs two comparisons. The first comparison tests for
equality between the DMA address of the next buffer and the contents of the Page Stop Register. If the buffer
address equals the Page Stop Register, the buffer management logic will restore the DMA to the first buffer in the
Receive Buffer Ring value programmed in the Page Start Address Register. The second of comparison test between
the DMA address of the next buffer address and the contents of the Boundary Pointer Register. If the two values are
equal the reception is aborted. The Boundary Pointer Register can be used to protect against overwriting any area in
the receive buffer that has not yet been read. When linking buffers, buffer management will never cross this pointer,
effectively avoiding any overwrites. If the buffer address does not match either the Boundary Pointer or Page Stop
Address, the link to the next buffer is performed.
4000h
8000h
Page Start
Page Stop
1
2
3
4
…
n-2
n-1
n
Boundary Page
Current Page
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AX88796C 制造商:ASIX 制造商全稱:ASIX 功能描述:Low-Power SPI or Non-PCI Ethernet Controller
AX88796CLF 制造商:ASIX Electronics Corporation 功能描述:
AX88796L 制造商:ASIX 制造商全稱:ASIX 功能描述:3-in-1 Local Bus Fast Ethernet Controller
AX88796LF 制造商:ASIX 功能描述:10/100 MAC
AX88850 制造商:ASIX 制造商全稱:ASIX 功能描述:100BASE-TX/FX Repeater Controller
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