
ASIX ELECTRONICS CORPORATION
43
AX88796BLF / AX88796BLI
5.1.32 Current Page Register (CPR)
Page1 Offset 07H (Read/Write)
Field
Name
Description (Default = 4Dh)
7:0
CPR
The Buffer Management Logic as a backup register for reception uses this register
internally. CURR contains the address of the first buffer to be used for a packet reception
and is used to restore DMA pointers in the event of receive errors. This register is initialized
to the same value as PSTART and should not be written to again unless the controller is
Reset.
5.1.33 Multicast Address Register 0 (MAR0)
Page1 Offset 08H (Read/Write)
Field
Name
Description (Default = 00h)
7:0
MAR0
Multicast Address Register 0
5.1.34 Multicast Address Register 1 (MAR1)
Page1 Offset 09H (Read/Write)
Field
Name
Description (Default = 00h)
7:0
MAR1
Multicast Address Register 1
5.1.35 Multicast Address Register 2 (MAR2)
Page1 Offset 0AH (Read/Write)
Field
Name
Description (Default = 00h)
7:0
MAR2
Multicast Address Register 2
5.1.36 Multicast Address Register 3 (MAR3)
Page1 Offset 0BH (Read/Write)
Field
Name
Description (Default = 00h)
7:0
MAR3
Multicast Address Register 3
5.1.37 Multicast Address Register 4 (MAR4)
Page1 Offset 0CH (Read/Write)
Field
Name
Description (Default = 00h)
7:0
MAR4
Multicast Address Register 4
5.1.38 Multicast Address Register 5 (MAR5)
Page1 Offset 0DH (Read/Write)
Field
Name
Description (Default = 00h)
7:0
MAR5
Multicast Address Register 5
5.1.39 Multicast Address Register 6 (MAR6)
Page1 Offset 0EH (Read/Write)
Field
Name
Description (Default = 00h)
7:0
MAR6
Multicast Address Register 6
5.1.40 Multicast Address Register 7 (MAR7)
Page1 Offset 0FH (Read/Write)
Field
Name
Description (Default = 00h)
7:0
MAR7
Multicast Address Register 7