參數(shù)資料
型號(hào): AX88796BLI
廠商: ASIX Electronics Corporation
英文描述: Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
中文描述: 低引腳數(shù)的非PCI 16位產(chǎn)品10/100M自適應(yīng)快速以太網(wǎng)控制器
文件頁數(shù): 46/82頁
文件大?。?/td> 519K
代理商: AX88796BLI
ASIX ELECTRONICS CORPORATION
46
AX88796BLF / AX88796BLI
5.1.52 Wakeup Frame Offset (WFOFST)
Page3 Offset 07H (Read/Write)
Field
Name
Description (Default = 00h)
7:0
WF0OFST Byte mask Offset for wake-up frame filter 0. Host continue write 4 times to completed
32-bits of Byte Mask 3, 2, 1, 0 Offset. The unit is 16-bit. (2bytes)
15:8
WF1OFST Byte mask Offset for wake-up frame filter 1.
23:16
WF2OFST Byte mask Offset for wake-up frame filter 2.
31:24
WF3OFST Byte mask Offset for wake-up frame filter 3.
5.1.53 Wakeup Frame Last Byte (WFLB)
Page3 Offset 08H (Read/Write)
Field
Name
Description (Default = 00h)
7:0
WFLB0
Mask Last Byte for wake-up frame filter 0. Host continue write 4 times to completed
32-bits of Last Byte of 3, 2, 1, 0 filter.
15:8
WFLB1
Mask Last Byte for wake-up frame filter 1.
23:16
WFLB2
Mask Last Byte for wake-up frame filter 2.
31:24
WFLB3
Mask Last Byte for wake-up frame filter 3.
5.1.54 Wakeup Frame Command (WFCMD)
Page3 Offset 09H (Read/Write)
Field
Name
Description (Default = 00h)
3:0
WFCMD0 Byte Mask Command for wake-up frame filter 0. Host continue write 4 times to completed
32-bits of Byte Mask Command of 3, 2, 1, 0 filter and Mask cascade commend.
Bit0: wake-up frame filter enable
Bit1: destination match enable
Bit2: Multicast match enable
Bit3: Reserved
7:4
WFCMD1 Byte Mask Command for wake-up frame filter 1.
11:8
WFCMD2 Byte Mask Command for wake-up frame filter 2.
15:12
WFCMD3 Byte Mask Command for wake-up frame filter 3.
19:16
WFCSCD Byte Mask Cascade Command for wake-up frame filter
Bit-0: cascade wake-up filter 1 and 0
Bit-1: cascade wake-up filter 2 and 1
Bit-2: cascade wake-up filter 3 and 2
31:18
-
Reserved. Always zero.
5.1.55 Wakeup Control and Status Register (WUCSR)
Page3 Offset 0AH (Read/Write)
Field
Name
Description (Default = 00h)
7
-
Reserved
6
LSC
Link status change event flag. This bit will be clear when Host write PMR or set this bit.
5
WUFR
Wake-up Frame Received event flag. This bit will be clear when Host write PMR or set
this bit.
4
MPR
Magic Packet Received event flag. This bit will be clear when Host write PMR or set this
bit.
3
-
Reserved
2
LSCWE
Link status change wakeup enable
0: disable (Default)
1: enable
1
WUEN
Wake-up frame enable
0: disable (Default)
1: enable
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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