參數(shù)資料
型號: AX88796BLI
廠商: ASIX Electronics Corporation
英文描述: Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
中文描述: 低引腳數(shù)的非PCI 16位產品10/100M自適應快速以太網(wǎng)控制器
文件頁數(shù): 71/82頁
文件大?。?/td> 519K
代理商: AX88796BLI
ASIX ELECTRONICS CORPORATION
71
AX88796BLF / AX88796BLI
7.4.5 Burst Reads Access Timing
Burst read access is enabled when set FIFO_SEL(SA5) is driven high during a read access. This is normally
accomplished by connecting the FIFO_SEL(SA5) signal to a high-order address line. This mode is useful when
the host processor must increment its address when accessing the AX88796B.
In this mode, performance is improved by allowing an unlimited number of back-to-back WORDS read cycles.
AX88796B base on SA0 or SA1 address toggles to identify WORD access cycle time. Host can set burst cycle
base on SA0 or SA1 toggle by BCB1 (CR page3 Offset 0Dh).
Tdoff
Tdoh
Tadv
Tadv
Tadv
Tdv
Tdon
Trdh
Tah
Tasu
Tacyc
Tacyc
Tacyc
FIFO_SEL(SA5)
SA1 or SA0
CSn, RDn
SD[15:0]
Symbol
Tasu
Tah
Tdv
Description
Min
0
0
-
Typ.
-
-
-
Max
-
-
33*
1
35*
2
33*
1
35*
2
-
-
7
Units
ns
ns
ns
ADDRESS SETUP TIME
ADDRESS HOLD TIME
DATA VALID TIME FROM RDn
Tadv
DATA VALID TIME FROM ADDRESS
ns
Tdoh
Trdh
Tacyc
Tdon
Tdoff
DATA OUTPUT HOLD TIME
RDn HI REQUIRE TIME
READ CYCLE TIME
DATA BUFFER TURN ON
DATA BUFFER TURN OFF
0
13
48
0
-
-
ns
ns
ns
ns
ns
*
1
: Base on SD bus output load 25pF
*
2
: Base on SD bus output load 50pF
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相關代理商/技術參數(shù)
參數(shù)描述
AX88796C 制造商:ASIX 制造商全稱:ASIX 功能描述:Low-Power SPI or Non-PCI Ethernet Controller
AX88796CLF 制造商:ASIX Electronics Corporation 功能描述:
AX88796L 制造商:ASIX 制造商全稱:ASIX 功能描述:3-in-1 Local Bus Fast Ethernet Controller
AX88796LF 制造商:ASIX 功能描述:10/100 MAC
AX88850 制造商:ASIX 制造商全稱:ASIX 功能描述:100BASE-TX/FX Repeater Controller