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參數(shù)資料
| 型號： | AX88796BLI |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller |
| 中文描述： | 低引腳數(shù)的非PCI 16位產(chǎn)品10/100M自適應(yīng)快速以太網(wǎng)控制器 |
| 文件頁數(shù)： | 17/82頁 |
| 文件大?。?/td> | 519K |
| 代理商： | AX88796BLI |
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ASIX ELECTRONICS CORPORATION
17
AX88796BLF / AX88796BLI
Linking Buffers
Before the DMA can enter the next contiguous 256 bytes buffer, the address is checked for equality to PSTOP and
to the Boundary Pointer. If neither is reached, the DMA is allowed to use the next buffer.
Buffer Ring Overflow
If the Buffer Ring has been filled and the DMA reaches the Boundary Pointer Address, reception of the current
incoming packet will be discard by the AX88796B. Thus, the packets previously received and still contained in the
Ring will not be destroyed.
End Of Packet Operations
At the end of the packet the AX88796B determines whether the received packet is to be accepted or rejected. It
either branch to a routine to store the or to another routine that recovers the buffers used to store the packet.
If current of packet is accepted then AX88796B write two words of buffer header on receive buffer.
Buffer Header
NPR, Status
Description
D[15:8]: Next Page Pointer
D[7:6]: always zero
D[5]: multicast or broadcast
D[4]: runt packet
D[3]: MII error
D[2]: alignment error
D[1]: CRC error
D[0]: good packet
D[15:11]: always zero
D[10:0]: packet length
Length
Successful Reception
If the packet is successfully received as shown, the DMA is restored to the first buffer used to store the packet
(pointed to by the Current Page Register). The DMA then stores the Receive Status, a Pointer to where the next
packet will be stored and the number of received bytes. Note that the remaining bytes in the last buffer are discarded
and reception of the next packet begins on the next empty 256 byte buffer boundary. The Current Page Register is
then initialized to the next available buffer in the Buffer Ring. (The location of the next buffer had been previously
calculated and temporarily stored in an internal scratchpad register.)
Buffer Recovery For Rejected Packets
If the packet is a runt packet or contains CRC or Frame Alignment errors, it is rejected. The buffer management
logic resets the DMA back to the first buffer page used to store the packet (pointed to by CPR), recovering all
buffers that had been used to store the rejected packet. This operation will not be performed if the AX88796B is
programmed to accept either runt packets or packets with CRC or Frame Alignment errors. The received CRC is
always stored in buffer memory after the last byte of received data for the packet.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AX88796C | 制造商:ASIX 制造商全稱:ASIX 功能描述:Low-Power SPI or Non-PCI Ethernet Controller |
| AX88796CLF | 制造商:ASIX Electronics Corporation 功能描述: |
| AX88796L | 制造商:ASIX 制造商全稱:ASIX 功能描述:3-in-1 Local Bus Fast Ethernet Controller |
| AX88796LF | 制造商:ASIX 功能描述:10/100 MAC |
| AX88850 | 制造商:ASIX 制造商全稱:ASIX 功能描述:100BASE-TX/FX Repeater Controller |
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