參數(shù)資料
型號： AX88796BLI
廠商： ASIX Electronics Corporation
英文描述： Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
中文描述： 低引腳數(shù)的非PCI 16位產(chǎn)品10/100M自適應快速以太網(wǎng)控制器
文件頁數(shù)： 6/82頁
文件大小： 519K
代理商： AX88796BLI
ASIX ELECTRONICS CORPORATION
6
AX88796BLF / AX88796BLI
2.0 Signal Description
The following abbreviations are used in AX88796B pinout:
All pin names with the “n” suffix are low-active signals.
The following abbreviations are used in following Tables.
I Input 1.8V
O Output 1.8V
I5 Input 3.3V with 5V tolerant
O5 Output 3.3V with 5V tolerant
T5 Tri-state with 5V tolerant
B5 Bi-directional I/O, 3.3V with 5V tolerant
4m 4mA driving strength
2.1 Local CPU Bus Interface Signals Group
Signal
Type
Pin No.
SA[4:0]
SA[5] or
FIFO_SEL
8m 8mA driving strength
S Schmitt trigger
PU Internal Pull Up 75Kohm
PD Internal Pull Down 75kohm
P Power Pin
A Analog
Description
I5
46, 47, 48, 49,
50
45
System Address: Signals SA[4:0] are address bus input lines. Used to
select internal CSR’s.
System Address or FIFO Select: When driven high, all accesses to the
AX88796B are to the RX or TX data buffer FIFO (DP).
AX88796B supports two kinds of Data Port for receiving/transmitting
packets from/to AX88796B. One is the PIO Data Port (offset 10h);
the other one is the SRAM-like Data Port (e.g. offset 800h ~ FFFh for
Samsung2440 processor as described in Appendix A4 of AX88796B
datasheet). The SRAM-like Data Port address range depends on
which address line of host processor is being connected to the address
line SA5/FIFO_SEL of AX88796B.
Software on host CPU can issue Single Data Read/Write command to
both PIO Data Port and SRAM-like Data Port. However, to use Burst
Data Read/Write commands, one has to use SRAM-like Data Port,
which requires SA5/FIFO_SEL (pin 45) of AX88796B connecting to
an upper address line of host CPU. Our reference schematic has
SA5/FIFO_SEL pin connected to upper address line for supporting
Burst Data Read/Write commands.
System Data Bus: Signals SD[15:0] constitute the bi-directional data
bus.
I5/PD
SD[15:0]
B5/8m
27, 28, 29, 30,
31, 32, 33, 34,
35, 36, 37, 38,
39, 40, 41, 42
23
IRQ
O5/T5/8m
Programmable Interrupt request. Programmable polarity, source and
buffer types.
Can be configure by EEPROM auto-loader or BTCR (offset 15h)
Chip Select: Active low.
Read: Active low strobe to indicate a read cycle.
Write: Active low strobe to indicate a write cycle. This signal also
used to wakeup the AX88796B when it is in reduced power state.
16 Bit Port: For ISA bus used. The IOIS16n is asserted when the
address at the range corresponds to an I/O address to which the chip
responds, and the I/O port addressed is capable of 16-bit access.
Address Enable: When 186, ISA mode, this signal is active low to
access AX88796B.
PSEN: When 51 modes, this signal is active high to access
AX88796B.
CSn
RDn
WRn
IOIS16n
I5
I5
I5
52
53
54
T5/8m
55
AEN or PSEN
I5
51
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
AX88796C 制造商:ASIX 制造商全稱:ASIX 功能描述:Low-Power SPI or Non-PCI Ethernet Controller
AX88796CLF 制造商:ASIX Electronics Corporation 功能描述:
AX88796L 制造商:ASIX 制造商全稱:ASIX 功能描述:3-in-1 Local Bus Fast Ethernet Controller
AX88796LF 制造商:ASIX 功能描述:10/100 MAC
AX88850 制造商:ASIX 制造商全稱:ASIX 功能描述:100BASE-TX/FX Repeater Controller
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